GPIO questions

Zheng Zhao said:

Hi All,

I would like to ask a question on GPIO.

In document SPRU988b, page 22-27, register definition for

1. OUT_DATAn
2. SET_DATAn
3. CLR_DATAn

are listed.

In the output mode, if SET_DATAn and CLR_DATAn are already sufficient to determine the value of the pin, is OUT_DATAn redundant? Why is it still provided?

Section 1 of SPRU988 gives a decent description of why the SET and CLR registers are provided to the application.  This reason is to provide a mechanism to allow multiple software processes to control GPIO signals without a critical section protection which would be required in a read-modify-write situation.

The OUT register is also provided as another means of controlling the state of the GPIO when configured as an output.

Yes, it is "redundant" but having both gives the application flexibility on how it can control the GPIO.

I would not agree with the statement that the SET_DATAn and CLR_DATAn are sufficient to "determine" the value of the pin.  This is what the INPUT register is for.  Look at Figure 1 as it helps illustrate what controls what.

Zheng Zhao said:

Another question is on the terminology used in GPIO’s register description:

 

       

What does

1. Determine
2. Driving high
3. Driving low

mean, respectively? Again, doesn’t “determine” include “driving high” and “driving low”? Isn’t it redundant?

Thanks,
Zheng

Refer to Section 2.6 of SPRU988.

Determine : the processor can write to the register to set the GPIO high or low.
Driving high : the processor sets the GPIO high by writing a 1 to the appropriate bit in the SET register.
Driving low : the processor sets the GPIO low by writing a 1 to the appropriate bit in the CLR register.

Actually, Section 3.6 and 3.7 indicate a read of the SET and CLR registers returns the output drive state of the corresponding GPIO pin.

Zheng,

These registers are not really redundant since their purpose is to allow you to either set or clear a specific bit (or bits) on a port without needing to read the current setting for the port register first.

Without the set and clear registers it would be necessary to first read the GPIO register, then either set or clear the corresponding bit then write the result back to the GPIO register.

With the set and clear registers you can, for example, set bits 3 and 6 of the output port simply by setting bits 3 and 6 in the 'set' register without reading and masking bits.

BR,

Steve

hi Zheng

ok, Ultimate aim is to provide flexibility to programmer, with at least instructions.

regards

nikhil