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How to set FP/Sync/BP for TI OMAP3 @ 1280*1024

hb chen
Expert 2640 points
Other Parts Discussed in Thread: OMAP3530

Dear Experts,

OS: WinCE / Platform: OMAP3530

 TI OMAP3 can support 1280*1024 resolution @ ~44Hz.

But I can't find this mode @ VESA Monitor Timing Specification.

And most monitor should not support this frequency. = =?? ~

How do I set the  FP/Sync/BP for TI OMAP3 @ 1280*1024  @ ~44Hz and How to verify that  ??

thx ~

 

Reference Link: http://processors.wiki.ti.com/index.php/Display_Subsystem

"The output pixel frequency can be up to 75MHz, supporting various resolutions and frame rates. "

http://processors.wiki.ti.com/images/thumb/c/cc/OMAP3_LCD_sizes.jpg/400px-OMAP3_LCD_sizes.jpg

=======================================

Some definitions in WinCE code.

#define INDEX_LCD_PIXELTYPE        0

#define INDEX_LCD_WIDTH            1 ==>1280

#define INDEX_LCD_HEIGHT           2==>1024

#define INDEX_LCD_HSW              3==>??

#define INDEX_LCD_HFP              4==>??

#define INDEX_LCD_HBP              5==>??

#define INDEX_LCD_VSW              6==>??

#define INDEX_LCD_VFP              7==>??

#define INDEX_LCD_VBP              8==>??

#define INDEX_LCD_LOGCLKDIV        9==>??

#define INDEX_LCD_PIXCLKDIV        10==>??

#define INDEX_LCD_LOADMODE         11

#define INDEX_LCD_POLFREQ          12==>??

#define INDEX_LCD_DEFAULT_COLOR    13

#define INDEX_LCD_TRANS_COLOR      14

#define INDEX_TV_DEFAULT_COLOR     15

#define INDEX_TV_TRANS_COLOR       16

#define INDEX_DSS_CLKSEL_DSS1      17

=======================================

  • 0
    Mastermind 9310 points

    Hi,

    The OMAP3 DSS display controller should support this kind of resolution as long as the connected display is compatible. By default the BSP does not provide this resolution (maximum is 1024x768), you would then have to create a new mode under :

    WINCE600\PLATFORM\EVM_OMAP3530\SRC\BSP_COMMON\DISPLAY\lcd_vga.c

    A mode is defined by the OMAP_LCD_DVI_RES_PARAMS structure from where you have to provide resolution, frequency, fp, bp, timings and so on. Timings are dependent on the display, you might find them in your display's datasheet.

  • 0 in reply to Adeneo Embedded support team
    Expert 2640 points

    Thx,

    I didn't get the display's datasheet. But I try a setting as bellow, it can show some area at my 7" LCD Display (800x480) through LVDS.

    //5: 1280x1024@ ~40hz, ~72Mhz pixel clock, // LCD_MODE_1280_1024_40HZ

    { DISPC_PIXELFORMAT_RGB16,1280,1024,63,103,255,1,3,30,1,2,0,

        DISPC_POL_FREQ_ONOFF,0x00000000,0x00000000,0x00000000,0x00000000,(6 << 0)},

     

    However, this setting can't display to my PC monitor through VGA port. (Most Monitors require at least 50Hz)

     

  • 0 in reply to hb chen
    Mastermind 9310 points

    hb chen said:

    { DISPC_PIXELFORMAT_RGB16,1280,1024,63,103,255,1,3,30,1,2,0,

        DISPC_POL_FREQ_ONOFF,0x00000000,0x00000000,0x00000000,0x00000000,(6 << 0)},

    It seems the structure above is wrong as your "dss1ClkSel" parameter seems to be last position where it should upper in the list. Anyway it is probably a copy/paste issue. Comments in lcd_vga.c say that dss1ClkSel can be set as low as 5 at nominal voltage. You could try this divider and get a pixel clock of 86 MHz which would give you a framerate around 60 Hz. I don't know if this is a supported scenario but it could be worth givinig it a try.

  • 0 in reply to Adeneo Embedded support team
    TI__Mastermind 43875 points

    Since this is a non standard resolution there are no standard settings for the blanking times.

    I would, however, try starting with the standard VESA settings for 1280x1024 then reduce the blanking timings in multiples of 4 clocks horizontally and 1 line vertically to see if any settings work.

    You can use the web page at http://www.epanorama.net/faq/vga2rgb/calc.html to determine the initial settings.

    If you are able to directly change registers then you can change the blanking settings directly then set to GOLCD bit to test each blanking setting rather than re-compiling the kernel for every change.

    BR,

    Steve

  • 0 in reply to Adeneo Embedded support team
    Expert 2640 points

    Dear Adeneo Embedded support team,

    In lcd_vga.c, there seems a formula to calculate PixelClock:

    LcdPdd_LCD_GetMode { 

    ...

    if ( pPixelClock )

        { *pPixelClock = (864000000 / g_LcdMode[g_iIndexLcdMode][INDEX_DSS_CLKSEL_DSS1]) / g_LcdMode[g_iIndexLcdMode][INDEX_LCD_PIXCLKDIV]; }}

    The maximum pixel clock of OMAP 3530 is ~75Mhz, so I set DSS_CLKSEL_DSS1=6 and LCD_PIXCLKDIV=2 to match 72MHz (75MHz ↓).

    Did you mean I could modify DSS_CLKSEL_DSS1 from 6 to 5 to get a 86MHz Pixel Clock to try ??

     

     

     

  • 0 in reply to hb chen
    Mastermind 9310 points

    From the following comment under lcd_vga.c:

    lcd_vga.c said:

    // Allowed values: BSP_DSS_CLKSEL_DSS1 minimum value is 5 (173 MHz) at nominal voltage

    //                          BSP_DSS_CLKSEL_DSS1 minimum value is 9 (96 MHz) at low voltage

    //                          BSP_DSS_CLKSEL_TV should be fixed at 16 (54 MHz)

     

    It actually conflicts with your information of a maximum 75 MHz for the pixel clock, moreover it does not seem to be a reliable source. I don't know where you got your 75MHz limit from, if you feel like your source is more reliable, then you should not try to set the pixel clock over 75 MHz with a divider of 5.

  • 0 in reply to Adeneo Embedded support team
    Expert 2640 points

    Dear Adeneo Embedded support team,

    75MHz limit is for pixel clock from http://processors.wiki.ti.com/index.php/Display_Subsystem

    DSS1 = DPLL4 / BSP_DSS_CLKSEL_DSS1, Note: DPLL4 is 864Mhz

    pixel clock = ( DPLL4(864Mhz) / BSP_DSS_CLKSEL_DSS1 ) / BSP_LCD_PIXCLKDIV  <= 75Mhz ??  Is it right ??~ or I miss the meaning of pixel clock ~??

    for example, the comments under lcd_vga.c:

    #elif BSP_DVI_1280W_720H

        #define BSP_DSS_CLKSEL_DSS1        (6 << 0)     // DSS1 = DPLL4/6 = 144Mhz

        #define BSP_LCD_PIXCLKDIV          2            // pixel clock = 72MHz

    ==> ( 864MHz / 6 ) / 2 = 72MHz = pixel clock

  • 0 in reply to hb chen
    Mastermind 9310 points

    You are right, the BSP as-is does not use a pixel clock higher than 75 MHz. It seems however than you need more than this to achieve a framerate bigger than 40 Hz for your 1280x1024 resolution (which is the point of this post). This is why I suggested you try with "#define BSP_DSS_CLKSEL_DSS1 (5 << 0) " to get a higher pixel clock, which seems to be supported according to the comments.

    From TI's wiki, it is clear that you should not use a pixel clock higher than 75MHz and this is why the output framerate will not be better than 40 KHz with a resolution of 1280x1024. To summarize, if your 1280x1024 display panel does not work under a framerate lower than 40 Hz it means that this panel cannot be supported by the OMAP3 processor.

     

  • 0 in reply to Adeneo Embedded support team
    TI__Mastermind 43875 points

    It is possible to reduce the blanking times to attain a higher frame rate, but this is also non-standard so there is no guarantee that any given monitor will actually display things correctly.

    The max pixel rate of 74.25MHz is a hardware design goal for the IO pins. There is usually margin, and I have been able to run the display output at about 85MHz, but this is out of the design specification for the chip.

    BR,

    Steve