Other Parts Discussed in Thread: TMS320VC5502
Hi,
I have a problem with SDRAM K4S281632K connected to the TMS320VC5502 DSP.
The initialization sequence is
#define SDRAM_TRC 0x06 // 0x0F
#define SDRAM_TRCD 0x02 // 0x04
#define SDRAM_TRP 0x01 // 0x08
UINT16 SDWIDTH;
// Xilinx setup
CE0_1 &= ~0x00F0;
CE0_1 |= 0x09 << 4; // Memory type - 16 bit SDRAM
// EMIF SDRAM Control 1
// enable self refresh, Trc - max - 0x0F
//SDC1 = ( SDRAM_TRC << 12 )| 0x01;
SDC1 = ( SDRAM_TRC << 12 );
// EMIF SDRAM Control 2
// SDWIDTH[4..0]
// bit 4 - 1 -- 4 banks
// bit 3..2 - 01 -- 12 raw address pins
// bit 1..0 - 00 -- 9 column address pins
// 10100 0x14
SDWIDTH = ( 1 << 4 )|( 1 << 2 ); // 4 banks, 12 raw addr. pins 9 column
// Enable self-refresh TRCD - 0x04 TRP - 0x08;
SDC2 = ( SDWIDTH << 10 )|( 1 << 9 )|( SDRAM_TRCD << 0x04 )| SDRAM_TRP ;
CESCR1 = 0x01; // CE0: 0x000000-0xFFFFFF
SDX1 &= ~1;
// starting SDRAM
SDC2 |= ( 1 << 8 );
K4S281632K — 16 bit, 4 banks, 12 rows and 9 coloms SDRAM memory.
The initialization seems proper.
During the test I write sequence counter from the chip's start address.
But instead of reading «0, 1, 2, 3, 4, 5, 6, 7», I read «0, 3, 0, 5, 0, 7, 0, 9 ».
Is there any idea about it? Does anybody have an SDRAM initialization example?
