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CCS/TDA3XEVM: memory access from IPU to DSP

robert2012
Intellectual 700 points
Part Number: TDA3XEVM


Tool/software: Code Composer Studio

HI

I am a learner on TDA3xevm ,

I am working on a usecase like this nullsrc->algorithm on dsp->display

I  read a yuv file and then do fd and display the picture, according to the PROCESSOR_SDK_VISION_03_07_00_00\vision_sdk\apps\src\rtos\usecases\null_src_display usecase.

I  have 2 questions:

1) there is no fileread api in this usecase, how can I read a file into memory (works on ipu1_0),

what can i use to allocate memory, ChainsCommon_Osal_memAlloc, OSA_memAllocSR  or Utils_memAlloc ?

2) how can I  pass the memory into dsp? (Do I need to transfer the memory space ?)

3) can I use malloc or new directyly  in algorithm which works on dsp?

Thanks!

  • 0
    TI__Genius 15985 points

    Hi,

    1. If you are not running linux on A15, then Filesystem support will be on IPU1_0, so you can read data from file only from IPU1_0, you can use Null_Src link for this.

    If you are using TI RTOS then ChainsCommon_Osal_memAlloc, OSA_memAllocSR   is of no use , you can use Utils_memAlloc  from any core to allocate memory.

    2. If you allocate memory using Utils_memAlloc  and pass the heap id as DR region, then you can pass pointer from ipu to DSP.

    3. Instead of malloc and new you have to use Utils_memAlloc  only, but here you have to provide local heap as your heap id.

    Please check implementation of Utils_memAlloc () function and check for all HEAP IDs.

    Regards,

    Anuj

  • 0 in reply to Anuj Gupta
    Intellectual 700 points

    HI  Anuj,

    Thanks for  your reply.

    I checked all the definitions in utils_mem_if.h,  Does DR region means UTILS_HEAPID_DDR_CACHED_SR? 

    Best Regards,

  • 0 in reply to robert2012
    TI__Genius 15985 points

    Hi,

    Sorry for the typo.

    It should be SR region and yes it should be UTILS_HEAPID_DDR_CACHED_SR.

    Regards,

    Anuj