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AM5728: DSP examples

Dirk Zenker
Intellectual 700 points
Part Number: AM5728


Hallo,

we are using the AM5728.

Actually we are running two bare metal applications on DSP1 and DSP2, that are using several peripherals (timer, eQEP, SPI) and are communicating with each other, with external slaves DSPs and via shared memory and mailbox with the Linux on the A15 cores.

Where can I find examples and CSL code for configuration of the cache (L1P/D), the bandwith management and the IDMA of the corepac?

Thank you.

Regards Dirk

  • 0
    Intellectual 700 points

    Hallo,

    I try to figure out, how fast running from L1-cache could be in comparison to running from L2 memory directly.

    I found no specification. The AM572x-TRM points to the CorePac-TRM. The CorePac-TRM refers to the device data sheet. At the device datasheet is noting specified.

    How many wait states has the L2 when using as memory (not as cache)?

    Since I found no specification I try at the next step to use the L1 cache to see how fast it is in comparision with L2 memory.

    At the AM572X-TRM (SPRUHZ6L) is written:

    "For more information on the TMS320C66x DSP CorePac, refer to the TMS320C66x DSP CorePac User
    Guide, ( SPRUGW0C), the TMS320C66x DSP Cache User Guide, ( SPRUGY8) and the TMS320C66x
    DSP CPU and Instruction Set Reference Guide, ( SPRUGH7)."

    When I study the TMS320C66x DSP Cache User Guide, ( SPRUGY8) I found the following chapter that describes how to configure the cache:

    "2.1 Configuring L1 Caches

    The configuration at boot time depends on the particular C66x device. The device may boot up as cache only, SRAM only, or a combination of each. See your device-specific data manual. The L1P and L1D cache sizes can be changed in the program code by issuing the appropriate chip support library (CSL) commands:

    CACHE_L1pSetSize();

    CACHE_L1dSetSize();"

    But this API does not exist. I searched through the CLS and use now the API

    DSPICFGCacheEnable( SOC_DSP_ICFG_BASE, DSPICFG_MEM_L1D, DSPICFG_CACHE_SIZE_L1_32K );

    DSPICFGCacheEnable( SOC_DSP_ICFG_BASE, DSPICFG_MEM_L1P, DSPICFG_CACHE_SIZE_L1_32K );

    DSPICFGSetMAR(SOC_DSP_ICFG_BASE, Addr, DSPICFG_MAR_PC);

    but the result was not like expected. Absolutely no acceleration.

    So how fast is the L2 memory and how to configure the L1 cache?

    Thank you.

    Regards Dirk

  • 0 in reply to Dirk Zenker
    TI__Mastermind 29778 points

    Hi Dirk,

    CSL API documentation is available in <PDK>\packages\ti\csl\docs\doxygen\index.html.

    I browsed through AM57xx PRSDK 6.1.0.8. From what I can determine:

    • BWM: no CSL code for AM57xx. I see "csl_pwmngmt.h", but this only compiles for SOC_C6678 & SOC_C6657. It may be possible to use this for AM57xx C66x.
    • IDMA: no CSL code for AM57xx. I see an example in <PDK>\packages\ti\csl\example\idma, but it doesn't build for AM57xx. It may be possible to use this for AM57xx C66x.
    • Cache: you've already identified some of the CSL function located in arch/c66x/dsp_icfg.h.

    Since DSPICFG_MAR_PC is defined as '1', it seems like you're enabling the L2 cache rather than disabling it. Have you checked all the L1/L2 cache registers after executing your code to verify the register are what you expect?

    Below is the best document I've been able to locate concerning AM572x (DRA72x) benchmarking.

    Regards,
    Frank

    sprac46_DRA7_Benchmarking.pdf