This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRA78XEVM: Shared Memory access

Part Number: DRA78XEVM

Hello,

I am planning to run one RTOS  to control all the required  tasks on all cores ?

Is this a good approach and on which core I need to run the RTOS ?

This approach will make it easier to control which core can access what resource at what time to minimize any conflict. 

Is this OK ?

I need to setup several  shared memory buffers where all cores can access and exchange data ?

Is this possible.  Any documentation to help with this setup

Other than shared memory access, what other options available for exchange of data between various cores ?

I could use DMA between each core and the external DDR.

But how I can guard against any conflict of read or write by several cores at the same time.

Any help on these topics is very much appreciated.

Regards

Hatem

  • Hi,

    Are you planning to use VISION SDK?

    Please go through the docs of SDK.

    It will answer all your questions.

    Regards,

    Anuj

  • No I am not using Vision SDK.

    Sorry I should have mentioned this in the original posting.

    Regards

    Hatem

  • Hi,

    TI provides its own SDK for all TDA platforms.

    SDK handles communication between all cores, running RTOS on them,resource management

    If you are not using VSDK then you have to write your own SDK or infrastructure with your design.

    So in that we can not help as it will be your own design.

    Only document you can refer is platform specific TRM which will have information about all hardware IPs and different cores architecture etc.

    Regards,

    Anuj