J7 MCU domain how to handle " last mode" of VSYS_3V3 drop store last status of system?

TI recommends to monitor your system input voltage & implement a "Power Loss Early Warning" control to enable any processor house keeping (saving registers to memory, etc.) before a power down seq begins.

Actually, the J6Plus EVM PDN/SCH implements VBATT power loss "early  warning" by leveraging the capabilities of the 1st Stage Buck Controller (TPS43351-Q1). As the SCH & PDN snap-shots below show, the VLIM_12V0 (VBATT input after reverse voltage & current limiting input conditioning) is divided down by a R-divider network (R39 & R21). This allows the EN_TPS43351 net connected to ENA & ENB input pins to disable 1st Stage Controller as the VLIM_12V0 crosses below 4.02V threshold. The R-Div provides a dividing factor of 0.4232 to convert 4.02V to 1.7V = min VIH for ENA & ENB inputs. As a result, the power good signals (PGA & PGB) assert low immediately while the controller continues operating & supplying VSYS_3V3 input voltage to 2nd stage SoC PDN (TPS65917-Q1 & LP87565-Q1). This provides ~1ms of "early warning" to 2nd Stage PMICs and optionally to an SoC GPIO to begin power down house-keeping.

Once PMICs receive the "early warning/shutdown signal", a standard power down sequence (defined by the TPS65917-Q1's OTP settings) can begin executing an SoC recommended power down sequence. The min input voltage to 917 PMIC is 2.75V for internal digital state machine logic.  After crossing below 2.75V, the PMIC's internal state machine stops operating, digital control of the analog power resources stops and all voltage outputs are disabled & begin to discharge. We have measured & validated on the bench the PMIC OTP settings provide 179us of elapsed time from PORz assertion until the VDDSHV_3V3 supply rail (rail with fastest discharge across the group of mainly 3.3V supplies are disabled first in pwr down seq) ramps down below the min SoC domain input voltage. In fact, the total elaped time from PORz asserting low until the VSYS_3V3 supply crosses 2.75V is ~2.44ms which is sufficient time to complete recommended power down seq under full control of PMIC's digital state machine.

Hope these design & validation testing details meet your needs...:)

J6Plus EVM SCH snap-shot, pg 32 - zone 2D:

J6Plus EVM PDN snap-shot:

Power Down Scope Capture from OTP validation testing:

Regards,

Bill McCracken