CCS/AM3352: EDMA transfer issue

int32_t Radar_EDMA_Params_Init(void)
{
    EDMA3_DRV_Result result  = EDMA3_DRV_SOK;
    uint32_t chId1 = EDMA3_DRV_HW_CHANNEL_AD;
    uint32_t chId2 = EDMA3_DRV_HW_CHANNEL_FFT;
    uint32_t tcc1 = EDMA3_DRV_TCC_ANY;
    uint32_t tcc2 = EDMA3_DRV_TCC_ANY;

    uint32_t chId_ad[EDMA3_CHANNEL_NUM_AD];
    uint32_t chId_FFT[EDMA3_CHANNEL_NUM_FFT];

    uint32_t BRCnt = 0;
    int srcbidx = 0, desbidx = 0;
    int srccidx = 0, descidx = 0;
    uint32_t acnt;
    uint32_t bcnt;
    uint32_t ccnt;
    uint16_t i;
    uint32_t tmp = 0;
    uint8_t fpga_start = 1;

    EDMA3_DRV_SyncType syncType = EDMA3_DRV_SYNC_AB;
    EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0};

/* init AD channel edma*/

    acnt = ACNT;
    bcnt = BCNT_AD;
    ccnt = CCNT;
    BRCnt = BCNT_AD;

    srcbidx = 0;
    desbidx = ACNT;
    srccidx = 0;
    descidx = ACNT*BCNT_AD;

    result = Edma3_CacheInvalidate(dstBuff1, MAX_DEST1_SIZE);
    if(result != EDMA3_DRV_SOK)
    {
        Radar_log("\n Edma3_CacheInvalidate unsuccessful\n");
    }


    //申请主通道
    result = EDMA3_DRV_requestChannel (handle_edma_ad, &chId1, &tcc1,
                                          (EDMA3_RM_EventQueue)0,
                                          &callback1, NULL);
    if(result != EDMA3_DRV_SOK)
    {
        Radar_log("\n EDMA3_DRV_requestChannel failed\n");
    }
    else
    {
        paramSet.srcAddr = (uint32_t)(GPMC_ADDRESS+0x0A);
        paramSet.destAddr = (uint32_t)(dstBuff1);
        paramSet.srcBIdx = srcbidx;
        paramSet.destBIdx = desbidx;
        paramSet.srcCIdx = srccidx;
        paramSet.destCIdx = descidx;

        paramSet.aCnt = acnt;
        paramSet.bCnt = bcnt;
        paramSet.cCnt = ccnt;

        paramSet.bCntReload = BRCnt;

        //paramSet.linkAddr = 0xFFFFu;

        /* Reset opt field first */
        paramSet.opt = 0x0u;
        /* Src & Dest are in INCR modes */
        paramSet.opt &= 0xFFFFFFFCu;

        /* Program the TCC */
        paramSet.opt |= ((tcc1 << OPT_TCC_SHIFT) & OPT_TCC_MASK);

        /* Enable Intermediate & Final transfer completion interrupt */
        paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT);
        paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);

        /* AB Sync Transfer Mode */
        paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);

        /* Now, write the PaRAM Set. */
        result = EDMA3_DRV_setPaRAM (handle_edma_ad, chId1, &paramSet);
        if(result != EDMA3_DRV_SOK)
        {
            Radar_log("\n EDMA3_DRV_setPaRAM failed result is %d\r\n\n",result);
        }
        else
        {
            for(i = 0; i < EDMA3_CHANNEL_NUM_AD; i++)
            {
                chId_ad[i] = EDMA3_DRV_LINK_CHANNEL;
                result = EDMA3_DRV_requestChannel (handle_edma_ad, &chId_ad[i], NULL,
                                                   (EDMA3_RM_EventQueue)0,
                                                   &callback1, NULL);
                if(result != EDMA3_DRV_SOK)
                {
                    Radar_log("\n EDMA3_DRV_requestChannel AD %d failed result is %d\r\n\n",i,result);
                }
                else
                {
                    if(i < (EDMA3_CHANNEL_NUM_AD - 1))
                    {
                        paramSet.destAddr = (uint32_t)(dstBuff1+EDMA_AD_SIZE*2*(i+1));
                    }
                    else
                    {
                        paramSet.destAddr = (uint32_t)(dstBuff1);
                    }
                    result = EDMA3_DRV_setPaRAM (handle_edma_ad, chId_ad[i], &paramSet);
                    if(result != EDMA3_DRV_SOK)
                    {
                        Radar_log("\n EDMA3_DRV_setPaRAM link channel parames AD %d failed result is %d\r\n\n",i,result);
                    }
                }
            }
        }

        if(result == EDMA3_DRV_SOK)
        {
            result = EDMA3_DRV_linkChannel(handle_edma_ad, chId1, chId_ad[0]);
            for (i = 0; i < EDMA3_CHANNEL_NUM_AD; i++)
            {
                result = EDMA3_DRV_linkChannel(handle_edma_ad, chId_ad[i], chId_ad[(i+1)%32]);
            }
        }

        //event 22 is enabled
        //WR_MEM_32(EDMA_REG_BASE_ADDR+EDMA_REG_EESR_OFFSET, 1<<EDMA3_DRV_HW_CHANNEL_AD);

        if(result == EDMA3_DRV_SOK)
        {
            result = EDMA3_DRV_enableTransfer(handle_edma_ad,chId1,EDMA3_DRV_TRIG_MODE_EVENT);
            if(result == EDMA3_DRV_SOK)
            {
                Radar_log("\n EDMA3_DRV_enableTransfer successful\r\n");
            }
        }
        if(result != EDMA3_DRV_SOK)
        {
            Radar_log("\n EDMA3_DRV_enableTransfer failed  chId1 is %d  result is %d\r\n",chId1,result);
        }

        Radar_gpmc_write(&fpga_start, 1,0x16);// start fpga sampling data
    }
    return result;
}