TMS320C6747: Parallel NOR Flash Booting Process

Ambati,

It appears that you are using AIS NOR boot as described in the section 3.1.3 of the document here:

http://www.ti.com/lit/an/sprabb1c/sprabb1c.pdf

The direct mapped address for each chip select has a range of 32 MB as far as I can tell from the data sheet so there is no reason why the ROM should hang at 32 KB size.  How did you confirm that the image written to NOR flash is correct ? 

Also, indicate the value of Program counter when you connect to the DSP after the boot fails with image size >32 KB. If possible load the GEL file attached and proivde us the log so we can understand the SOC and ROM status when the image fails to load on the DSP.

3034.OMAPL1x_debug.gel 

Secondary bootloaders are basically user defined application boot code that execute from device RAM and loads the application. The ROM bootloader code on the device loads the secondary bootloader code and passes control to it. The secondary bootloader will then initialize the SOC as per application requirement and then load and run the application.

We provide example secondary bootloader in our Processor SDK RTOS software package as an example to use as a starting point.

Regards,

Rahul

PS: If possible, try to provide the part number of the parallel NOR that you are using and check if 32 KB Is the sector size and check the code that writes more than 32 KB to ensure that it is not over writing the code in the first sector  when image size >32 KB.