• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 98 subscribers
  • Views 568 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM3517 ZER package

paddu
Intellectual 915 points
Other Parts Discussed in Thread: AM3517

Hi,

 

This is a kind of basic question.

Will there be any difference in "ELECTRICAL CHARACTERISTICS" between 

ZCN(0.65mm pitch) and ZER(1mm pitch) packages?

Actually our customer is using the ZER package(XAM3517AZER) in their custom desing,

and they are having problems with DDR2 interface( which seems to be not working),

they have followed the desing guidlines from the datasheet and reference desing from LogicPD EVM.

As you know EVM uses the ZCN package, will there be any difference when using ZER packages.

 

Thankyou in advace

Regards.

  • 0
    TI__Mastermind 41665 points

    paddu said:

    Will there be any difference in "ELECTRICAL CHARACTERISTICS" between 

    ZCN(0.65mm pitch) and ZER(1mm pitch) packages?

    In general there should not be any electrical differences between package types of the same part, since the same silicon is used in the different packages, the only difference is the physical shape of the package itself. In the case of devices that may have some different electrical properties on a per package basis they would be called out specifically in the datasheet.

    In this case I am not aware of any particular electrical differences (though there are pinout differences) between the AM3517 ZER and ZCN packages, both packages use the same set of DDR layout guidelines. This being said, if the DDR2 does not seem to work properly, than it is likely worth reviewing the layout, often the guidelines are violated without the layout engineer necessarily realizing it, so a thorough review is often helpful. The most common point of failure I have come across in DDR2 layouts is crossing plane splits, it is important to ensure that all the DDR2 signals have a reference plane adjacent contiguously for the trace run, however there are other possible problems as well (keep out area violations, length matching violations, etc.). 

  • 0 in reply to Bernie Thompson TI
    Intellectual 915 points

    Thank you Bernie Thompson,

     

    I am new to hardware design, 

    and as the package size is changed from 0.65mm to 1mm pitch,I thought the DDR2 design might change.

     

    And regarding the configuration values of Termination,ODT,Drive Level,Impedance etc,

    should it be left as default.

    Is it possible to find out what kind of DDR2 related register settings are done in case of AM3517 EVM?

     

    Best  Regards.

  • 0 in reply to paddu
    TI__Mastermind 41665 points

    paddu said:
    Is it possible to find out what kind of DDR2 related register settings are done in case of AM3517 EVM?

    Certainly, the DDR configuration used on the EVM is defined within the X-Loader sources which are normally used to bring up the board, I would suspect for your custom board that you will be wanting to port X-Loader over to do your DDR initialization, which should probably be very similar if not identical depending on the DDR memory you use. The AM3517 software package (which includes the X-Loader sources) can be found at http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/sdk/AM3517/latest/index_FDS.html. Within this install you should be able to find the file AM35x-OMAP35x-PSP-SDK-03.00.00.05/src/boot-strap/x-loader-03.00.00.05/board/am3517evm/am3517evm.c which contains the DDR initialization code within the config_emif4_ddr() function. I have copied the contents of this function below for your convenience, the code is available under GPL v2.

    am3517evm.c said:

    /*********************************************************************
     * config_emif4_ddr() - Init/Configure DDR on AM3517 EVM board.
     *********************************************************************/
    void config_emif4_ddr(void)
    {
        unsigned int regval;

        /* Set the DDR PHY parameters in PHY ctrl registers */
        regval = (EMIF4_DDR1_RD_LAT | (EMIF4_DDR1_PWRDN_DIS << 6) |
            (EMIF4_DDR1_STRBEN_EXT << 7) | (EMIF4_DDR1_DLL_MODE << 12) |
            (EMIF4_DDR1_VTP_DYN << 15) | (EMIF4_DDR1_LB_CK_SEL << 23));
        __raw_writel(regval, EMIF4_DDR_PHYCTL1);
        __raw_writel(regval, EMIF4_DDR_PHYCTL1_SHDW);

        regval = (EMIF4_DDR2_TX_DATA_ALIGN | (EMIF4_DDR2_RX_DLL_BYPASS << 1));
        __raw_writel(regval, EMIF4_DDR_PHYCTL2);

        /* Reset the DDR PHY and wait till completed */
        sr32(EMIF4_IODFT_TLGC, 10, 1, 1);
        /*Wait till that bit clears*/
        while ((__raw_readl(EMIF4_IODFT_TLGC) & BIT10) == 0x1);
        /*Re-verify the DDR PHY status*/
        while ((__raw_readl(EMIF4_SDRAM_STS) & BIT2) == 0x0);

        sr32(EMIF4_IODFT_TLGC, 0, 1, 1);
        /* Set SDR timing registers */
        regval = (EMIF4_TIM1_T_WTR | (EMIF4_TIM1_T_RRD << 3) |
            (EMIF4_TIM1_T_RC << 6) | (EMIF4_TIM1_T_RAS << 12) |
            (EMIF4_TIM1_T_WR << 17) | (EMIF4_TIM1_T_RCD << 21) |
            (EMIF4_TIM1_T_RP << 25));
        __raw_writel(regval, EMIF4_SDRAM_TIM1);
        __raw_writel(regval, EMIF4_SDRAM_TIM1_SHDW);

        regval = (EMIF4_TIM2_T_CKE | (EMIF4_TIM2_T_RTP << 3) |
            (EMIF4_TIM2_T_XSRD << 6) | (EMIF4_TIM2_T_XSNR << 16) |
            (EMIF4_TIM2_T_ODT << 25) | (EMIF4_TIM2_T_XP << 28));
        __raw_writel(regval, EMIF4_SDRAM_TIM2);
        __raw_writel(regval, EMIF4_SDRAM_TIM2_SHDW);

        regval = (EMIF4_TIM3_T_RAS_MAX | (EMIF4_TIM3_T_RFC << 4) |
            (EMIF4_TIM3_T_TDQSCKMAX << 13));
        __raw_writel(regval, EMIF4_SDRAM_TIM3);
        __raw_writel(regval, EMIF4_SDRAM_TIM3_SHDW);

        /* Set the PWR control register */
        regval = (EMIF4_PWR_PM_TIM | (EMIF4_PWR_PM_EN << 8) |
            (EMIF4_PWR_DPD_EN << 10) | (EMIF4_PWR_IDLE << 30));
        __raw_writel(regval, EMIF4_PWR_MGT_CTRL);
        __raw_writel(regval, EMIF4_PWR_MGT_CTRL_SHDW);

        /* Set the DDR refresh rate control register */
        regval = (EMIF4_REFRESH_RATE | (EMIF4_PASR << 24) |
            (EMIF4_INITREF_DIS << 31));
        __raw_writel(regval, EMIF4_SDRAM_RFCR);
        __raw_writel(regval, EMIF4_SDRAM_RFCR_SHDW);

        /* set the SDRAM configuration register */
        regval = (EMIF4_CFG_PGSIZE | (EMIF4_CFG_EBANK << 3) |
            (EMIF4_CFG_IBANK << 4) | (EMIF4_CFG_ROWSIZE << 7) |
            (EMIF4_CFG_CL << 10) | (EMIF4_CFG_NARROW_MD << 14) |
            (EMIF4_CFG_CWL << 16) | (EMIF4_CFG_SDR_DRV << 18) |
            (EMIF4_CFG_DDR_DIS_DLL << 20) | (EMIF4_CFG_DYN_ODT << 21) |
            (EMIF4_CFG_DDR2_DDQS << 23) | (EMIF4_CFG_DDR_TERM << 24) |
            (EMIF4_CFG_IBANK_POS << 27) | (EMIF4_CFG_SDRAM_TYP << 29));
        __raw_writel(regval, EMIF4_SDRAM_CFG);

    }

  • 0 in reply to Bernie Thompson TI
    Intellectual 915 points

     

    Thank you Bernie Thompson,

     

    Please let me ask you one more clarification,

    are these register values recommended by TI or is it something which could be decided by the 

    customer by some test with their DDR memory.

    Is their any procedure to find out these values.

     

    Best Regards.

  • 0 in reply to paddu
    TI__Genius 9190 points

    Hello,

    Here is a good link on setting up the DDR interface for the AM3517:

    http://processors.wiki.ti.com/index.php/AM3517/05_SDRC_Subsystem

    in that link you will find a spreadsheet that will allow you to put in the datasheet values from the memory and it will give you the register values for the AC timings.