• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 163 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Queries related to McBSP configuration

Girisha SG
Intellectual 970 points
Other Parts Discussed in Thread: SYSCONFIG

I am having a sample test application. I make the process to sleep for 3 seconds and then exit. Below is the register configuration values(this process doesnot do anything other than this),

rcr2_reg   = 0x00000001;
rcr1_reg   = 0x000003A0;
xcr2_reg   = 0x00000001;
xcr1_reg   = 0x000003A0;
srgr2_reg   =  0x000010FF;
srgr1_reg   =  0x00001F00;
mcr2_reg   = 0x00000201;
mcr1_reg   = 0x00000201;
rcera_reg   =  0x0000000F;
rcerb_reg   =  0x00000000;
xcera_reg   =  0x0000000F;
xcerb_reg   =  0x00000000;
pcr_reg   = 0x00000F03;
sysconfig_reg  =  0x00000000;
thrsh2_reg   =  0x00000000;
thrsh1_reg   =  0x00000000;
irqenable_reg  =  0x00000000;
xccr_reg   =  0x00001008;
rccr_reg   =  0x00000808;

after this if I start some application that uses McBSP2 (if I run this application before then it works fine) I am observing noisy output
Can anyone please let me know the cause and solution for the same ?

  • 0
    TI__Mastermind 28115 points

    Girisha

    What is the configuration changes between it working and failing? How are you determining that you are seeing noise? Are you seing underflow errors?

    It would be helpful if you would detail what configuration you are trying to setup. From the above it looks like you are setting up a  frame of 4 x 32bit words with a frame sync of 32 bits and a frame period of 256 bits. Since this is a 4 pin McBSP you should set PCR.FSRM=0 and PCR.CLKRM=0 since the receiver will use the same signals as the transmitter (taken from the i/o pin). It also looks like your are setting up a multichannel configuration (MCRx)?

    Please provide some more detailed information.

      Paul

  • 0 in reply to PaulM
    Intellectual 970 points

    Yes I am observing undeflow errors. what would be the cause ?

    Also I have allocated a buffer of 1MB for storing the data, I am having 16 bits/audio sample & each frame is 3072 samples. Iwould like to allocate 1 channel & keep on sending the same buffer continuously(in chained transfer mode). I would like to get an interrupt after transferring every frame.

    What are the configuration of the ccr, cdf, csdp, cen, cfn, csr, cicr, clnk_ctrl register settings ?

  • 0 in reply to Girisha SG
    TI__Mastermind 28115 points

    Girisha

    Underflow is typically generated when the transmitter runs out of valid data.

    I would suggest that you set up a simple single DMA buffer with simple incrementing data values and loop that buffer to itself. Check that you see the expected data transmitted over the mcbsp TX line. also check that the format of the transmission is what you expect.

    Another option would be enter loopback mode and use the receive buffer to verify the transmitted data.  The example provided earlier will show you how to set this up.

    Another thing to check is that the mcbsp buffer thresholds are set appropriately. If the transmit threshold is to low then the Mobs may run out of data before the DMA can replenish the buffer.

    You currently have 4 threads open which appear to be on the same topic. Can we consolidate them into just one thread or are they independent questions?

    Some of the proposed debug is covered http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/p/85235/302987.aspx#302987

      Paul