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AM3358-EP: CPSW FIFO management

Part Number: AM3358-EP

Hi there,

I have a mature bare-metal application using the AM3358-EP and its Ethernet subsystem (SPRUH73Q TRM chapter 14).

I have some questions relating to the 3x CPSW_3G port RX FIFOs (1x host FIFO Port 0, and the 2x external FIFOs Ports 1 & 2).

At an arbitrary point in time with the Ethernet Subsystem sending and receiving typical Ethernet frames...

1) how can I ensure that new data is not passed into the 3x CPSW_3G port RX FIFOs?

2) how can I flush any existing data in the 3x CPSW_3G port RX FIFOs?

I'd like to change only what's necessary, accounting for any side-effects.

I understand a channel teardown will only prevent the DMA reading from the host FIFO to place into Buffer Descriptors.

I find Chapter Software Reset ambiguous, where many terms do not align with register addresses/descriptions.

With thanks, Mark

  • Hi,

    We are checking into the questions you asked.

    One to prevent new data from the RX FIFOs on the external CPSW ports is by setting in the CPSW_ALE REGISTERS section these registers PORTCTL1 and PORTCTL2 to blocked. These are bits 1-0 need to be set to a 1. 

    Concerning the flushing of the RX FIFO is what we are checking into.

    Best Regards,


  • Good morning Schuyler,

    Thank you for your response - I've been able to use the CPSW_ALE CONTROL register ENABLE_ALE bit to prevent new data entering the FIFOs.

    This, along with a reconfiguration of ALE registers (later), also appears to 'flush' the FIFOs.

    Many thanks, Mark