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Compiler/TMS320C6678: Memory writting problem

dariush karami
Genius 3165 points
Part Number: TMS320C6678


Tool/software: TI C/C++ Compiler

Hi

I want to write in DSP SRAM memory via SRIO by FPGA . When FPGA write in 0X10807E00 there isn't any problem but when write in 0X10800000 address if the Ethernet connected the program aborted!!!

I declared all memory segments in DDR3 section for avoiding any memory conflict.

Why this problem happened? please,guide me?

Best Regards

  • 0
    TI__Guru* 95265 points

    Hi,

    I don't see any relations:

    1) You declare all memory in DDR3, that means your code and program in DDR3, but you are accessing global L2 address by SRIO.

    2) Ethernet memory usage: does Ethernet using memory address 0x10800000 region? What do you mean connected? With cable connected and with traffic? What if with Ethernet initialized but without traffic?

    If you manually write 0x10800000 without using SRIO/FPGA, and with Ethernet connected, will program abort? Without Ethernet, can SRIO write to 0x10800000 without issue?

    Please elaborate details the TI software package, release, examples used when the issue occurred.

    Regards, Eric 

  • 0 in reply to lding
    Genius 3165 points

    Hi

    My problem solved by decelerating new memory sections and segments:

    I allocate the memory segments as below:

    My memory map is as below:

    Now I have a strange problem, In my board FPGA communicate with DSP by SRIO, I implemented my architecture as below:

    1)I dedicate "MSMCSRAM_Reserve" section for writing FPGA via SRIO.

    2) FPGA notify DSP by GPIO interrupt.

    3) I wan to read the "MSMCSRAM_Reserve" memory in my ISR.

    4) I ping the DSP Ethernet by my PC for testing Ethernet at the same time.

    When I write in the "MSMCSRAM_Reserve" in my ISR as below:

    SRIO works correctly, I check the :0x0C000000" in the memory browser, I see that the memory update correctly.

    But when I read from "MSMCSRAM_Reserve" in my ISR even one word as below:

    I see that SRIO stopped(I check the :0x0C000000" in the memory browser and the memory didn't update).

    I checked the signals of SRIO IP CORE in FPGA side and it seems correct, so I think there is some problem in DSP side.

    Please, help me to solve this problem,

    Best Regards

  • 0 in reply to dariush karami
    TI__Guru* 95265 points

    Hi,

    You declared a region in MSMC and this MSMC is cached into L1D. Now the FPGA writes the data into MSMC via SRIO, and you read it by CPU. The memory is not synced. The SRIO writes into the MSMC physical memory but CPU reads from the cache. You need do a cache invalidate before CPU read, inside your ISR,

    Regards, Eric 

  • 0 in reply to lding
    Genius 3165 points

    Hi

    Thanks a lot for your answer.

    Q1:

    I work with another board(FPGA+C6455) before, FPGA write in DSP by HPI, Why I don't have this problem in C6455?(I program one core in C6678 and

    I thought, I don't have cache coherency problem because I work with one core).

    Q2:

    Does I must invalidate in length of data that FPGA write in DSP?(FPGA write about 500KB data)

    Q3:

    Can you introduce some example or piece of code?(I don't work with cache invalidate functions)

    Regards

  • 0 in reply to dariush karami
    TI__Guru* 95265 points

    Hi,

    I am not sure about the HPI interface on C64x+, is it a master? In c6678, SRIO is a master. You can look at the memory region 0x0c00_0000 at CCS memory window with physical view or L1D, L2 cache checked/unchecked to determine what inside MSMC and what inside the cache, to see if this is the problem.

    If it is determined cache issue, you need to invalidate the length of the data.

    Some code example: you can refer to C6678 PDK package \ti\drv\pcie\example\sample\src\pcie_sample.c: cache_invalidate().

    Regards, Eric

  • 0 in reply to lding
    Genius 3165 points

    Hi

    Thank you, my problem solved.

    When we should use "Cache_invalid" or "cache_writeBack"...? Is there any reference or document about that?

    Best Regards