This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PROCESSOR-SDK-AM335X: DDR3 test

Part Number: PROCESSOR-SDK-AM335X
Other Parts Discussed in Thread: AM3358

Hi,

I am using AM335x board and TI RTOS SDK on windows host PC.

In GEL files whatever funtions are there, from where it is calling those functions. For example, StartUp() and OnTargetConnect().

Another thing is that after calling GEL_MapAddStr(0x80000000, 0, 0x40000000, "R|W", 0); , where it is going for definition?

In GEL File, one function is DDR_DataTransferCheck. Can I call this function in my main.c file to test the Power on Built test (PBIT) for external DDR3?

What are these function given below?

MMUConfigAndEnable();


CacheEnable(CACHE_ALL);

I want to write the data in RAM then how can I choose address in RAM?

I tried with below statements. In Disassembly window it should show data at particular below addresses but it is not showing. Data is printing on terminal. How can I confirm that it is writing to RAM only or working correctly?

*(unsigned int *)0x80004544 = 51;
*(unsigned int *)0x80004548 = 61;
unsigned int a,b;
a=*(unsigned int *)0x80004544;
b= *(unsigned int *)0x80004548;
ConsoleUtilsPrintf("a=%d, b=%d",a,b);

Regards

Gaurav

  • Hi Gaurav,

    The Startup() function in the GEL file is run when the debugger is launched.

    The OnTargetConnect() function is called when the target is connected

    GEL_MapAddStr adds one target memory map entry into the memory map for the ARM MMU (Memory Map Unit) 

    DDR_DataTransferCheck is a GEL function. You can call it from the CCS--> Scripts, but you cannot call it from your application code (like main())

    MMUConfigAndEnable is defined in ti_am3_610\pdk_am335x_1_0_16\packages\ti\osal\test\am335x\armv7\nonos\example_utils_mmu.c in Processor SDK RTOS 6.1.0 for AM335x

    CACHEEnable is defined in ti_am3_610\pdk_am335x_1_0_16\packages\ti\starterware\soc\cache_arm.c in Processor SDK RTOS 6.1.0 for AM335x

    When you run your program via CCS JTAG, the GEL file has set up the MMU (memory map) for you. The 0x80000000 is the beginning of the DDR. To see the contents of a memory area, you can use CCS --> View --> Memory Browser, then type in your memory address (for example, 0x80004544). You should see the contents of the memory area start with the address you typed in.

    If you want to run your application code via SBL, then the SBL will set up the memory map for you. Of course you can update the memory map in your application code too.

    Ming

  • Hi Ming,

    Thanks for your help.

    Are these functions "MMUConfigAndEnable and CACHEEnable" are necessary to call in application code because already memory mapping is done through GEL_MapAddStr in GEL file.

    In my application I am using MT41K256M16TW-107 DDR3 instead of MT41J128M16JT-125 (used in starter kit). Can I use same GEL file for my application?

    Can I access all 8 banks of external DDR3 in starter kit without changing any configuration in GEL file?

    Regards

    Gaurav

  • Hi Gaurav,

    If you only run the program from CCS JTAG, you do not need to configure MMU or cache, because the gel file will set them up for you. Eventually, you will need to run your program through bootloading from flash or SD card, then you will need the MMU and cache set up in SBL.

    Because MT41K256M16TW-107 is running at 933Mhz, while MT41J128M16JT-125 is running at 800Mhz, I think it should be OK for you to use the existing gel for starter kit.

    Ming

  • Yes, you can access all 8 banks of the DDR on starter kit with the current GEL file.

    Ming

  • Hi Ming,

    When I run my program through bootloading from flash, memory mapping will done by MMU and cache then SPL/MLO will take care of initialization of

    PLL, whatever it is done currently by GEL, right?

    Another thing, EMIF initialization will be done by MMU function, right? 

    Do I need to change configuration in MMU related to MT41K256M16TW-107 in my application because memory size and frequency is different from MT41J128M16JT-125?

    In GEL file, on target connect it is calling GEL_MapAddStr(0x80000000, 0, 0x40000000, "R|W", 0); for external memory mapping after that it will call AM3358_SK_Initialization();. How it is mapping memory before initialization?

    Can I see the definitions of in built functions like GEL_MapAddStr and WR_MEM_32 functions?

    Regards

    Gaurav

  • Hi Gaurav,

    When I run my program through bootloading from flash, memory mapping will done by MMU and cache then SPL/MLO will take care of initialization of

    PLL, whatever it is done currently by GEL, right?

    >> Yes.

    Another thing, EMIF initialization will be done by MMU function, right?

    >> EMIF configuration and MMU settings are two different things. 

    Do I need to change configuration in MMU related to MT41K256M16TW-107 in my application because memory size and frequency is different from MT41J128M16JT-125?

    >> As I mentioned before, the EMIF settings for MT41J128M16JT-125 (800Mhz) should work for  MT41K256M16TW-107 (933Mhz). It just not as efficient. The size changes are in MMU settings

    In GEL file, on target connect it is calling GEL_MapAddStr(0x80000000, 0, 0x40000000, "R|W", 0); for external memory mapping after that it will call AM3358_SK_Initialization();. How it is mapping memory before initialization?

    >> It should be either the power one reset values or ROM bootloader set values.

    Can I see the definitions of in built functions like GEL_MapAddStr and WR_MEM_32 functions?

    >> EMIF DDR settings are done in SBLPlatformDdrInit() of C:\ti_am3_610\pdk_am335x_1_0_16\packages\ti\starterware\bootloader\src\am335x\sbl_am335x_platform_ddr.c

    >> MMU settings are done in MMUConfigAndEnable() of C:\ti_am3_610\pdk_am335x_1_0_16\packages\ti\starterware\examples\example_utils\example_utils_mmu.c

    >> Cache settings are done in CACHEEnable() of C:\ti_am3_610\pdk_am335x_1_0_16\packages\ti\starterware\soc\cache_arm.c.

    Ming

  • Ming,

    Thanks for your answers.