This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi Experts:
At TDA4x schematic checklist request LPDDR4 reset signal add pull down resistor to ensure reset hold low during POR state.
But reference design E7 version add pull up resistor at LPDDR4 reset pin. (U11 pin T11)
It is conflict with schematic checklist. Could you please help us double check whether EVM design need optimize for LPDDR4 reset signal?
DNI R232 and place resistor at R228.
Best Regards!
Han Tao
Hi Han Tao,
The schematic checklist recommendation is beneficial in the common case.
However, if you plan to use a low power mode with main domain OFF, and DDR in self-refresh, then DDR reset must be pulled high, or other mechanism implemented to drive it high. Otherwise DDR will be in reset and will not be able to enter and maintain self-refresh so contents will be lost.
Regards,
Stan