hi,
I am making a EDMA to happen between source and dst buffer in the shared ram using the rcsl libray.I modified the timer Interrupt example provided with the rcsl to work with the EDMA. The EDMA is happening from source to dst buffer when i pool the IPR register.
as a next step i am trying to interrupt the ARM whith a Transfer Complete Interrupt.
I have ensured the following
I have mapped the DMA system interrupt to channel 2.(EVENT 11)
CSL_FINS(aintcRegs->CMR2, AINTC_CMR2_CHNL_NPLUS3, 2);
// Enable EDMA3 Interrupts
CSL_FINS(aintcRegs->EISR, AINTC_EISR_INDEX, AINTC_EVENTID_EDMA3_0_CC0_INT0);
/* Enable IRQ Interrupts */
CSL_FINS(aintcRegs->HIEISR, AINTC_HIEISR_INDEX, 1);
/* Enable Interrupts */
CSL_FINS(aintcRegs->GER, AINTC_GER_ENABLE, 1);
IPR.E0=1 & EESR.E0=1 and DRAE0.E0=1
but when i write the ESR register to trigger the event manually, The data transfer is happenning but the ISR is not hit.
is there something that i am missing
