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ARM-DSP Communication in OMAP L138

Other Parts Discussed in Thread: OMAP5910, OMAP-L138

Hi,

I'm a novice in this field. I would like to know how ARM-DSP communication is possible in OMAP L138. I have some idea about OMAP5910, where the ARM and DSP communicate via mailbox-interrupt mechanism. Is there anything similar to this possible in L138? 

A detailed response is highly appreciated.

Thanks

Jazir

 

  • The ARM and DSP interprocessor communication would be through a shared memory buffer and then interrupt mechanisms back and forth.  This is documented in the OMAP-L138 Applications Processor System Reference Guide (SPRUGM7).  See Section 11.4.

  • Hi Brandon,

     

    Thanks for the reply.

     

    In the document (SPRUGM7) it is mentioned that the SYSCFG module has a set of registers to facilitate interprocessor communication. Also ARM interrupts the DSP when it has to send data to the DSP using shared memory.

     

    I have the following questions on how to implement the interprocess communication.

     

    1) Which are the registers in SYSCFG module that facilitates interprocessor communication?

     

    2) Which are the corresponding interrupts in ARM & DSP side?

     

    Jazir

  • I want to let you know that TI has a software framework package called DSPLink (or the most recent version called SYSLINK) that was created to support Inter-Processor communication on a number of devices, including OMAP-L138.  This is included in our Linux Software Development Kit (SDK).  This IPC software is coupled with our DSP/BIOS RTOS.

    A list of all Software Development Kits is here.

     

    That said, I'll answer your specific questions.

    Jazir Hameed said:

    In the document (SPRUGM7) it is mentioned that the SYSCFG module has a set of registers to facilitate interprocessor communication. Also ARM interrupts the DSP when it has to send data to the DSP using shared memory.

    It also goes on to indicate a typical use-case scenario that highlights what these registers really are.  Essentially the registers contains bits that can be used by the DSP and ARM to generate interrupts for the other processor.  The "message" would be in a shared memory buffer that both processors have a priori knowledge of.  If I recall correctly, the OMAP5910 had a FIFO memory type of structure in between the 2 processors, where as the OMAP-L138 does not.  In the OMAP-L138, both the ARM and the DSP have access to external DRAM and other memory interfaces to facilitate the message queue between them.

     

    Jazir Hameed said:

    1) Which are the registers in SYSCFG module that facilitates interprocessor communication?

    These registers are documented in Section 11.5 of SPRUGM7 as the CHIPSIG (Chip Signal Register) and CHIPSIG_CLR (Chip Signal Clear Register), Section 11.5.12 and Section 11.5.13 respectfully.

     

    Jazir Hameed said:

    2) Which are the corresponding interrupts in ARM & DSP side?

    Section 11.5.12 indicates which interrupts these correspond to on the ARM and DSP side.

     

  •  

    Thank you very much Brandon for the details..

  • Hi,

    Where can I find the SPRUGM7 document? Also, where can I find samples of this type of communication? I want to interrupt ARM from DSP outside DSPLink.


    Thank you.

  • The mentioned details are somehow not there in SPRUGM7. I could not not find the 11.4 section as there are only 6 sections in it.

    Alternately I found interrupt driven ARM-DSP communication details can be in spruh77a.pdf.

    In the section 11.4 there are the required details.

    The link for the SPRUH77A.pdf

    http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf

    Please share if have more details on the ARM-DSP communication in OMAP-L138.

  • Hi,

    The document which I referred for ARM-DSP communication in OMAP L138 is 'SPRUGM7D' (OMAP-L138 Applications Processor System Reference Guide). Section 11.4 introduces the procedure. The major points are as follows.

    1) The interprocessor communication is facilitated by a set of registers in SYSCFG module. 

           CHIPSIG Register - To generate the interrupt  ( section 11.5.12)

           CHIPSIG_CLR Register - To clear the interrupt. ( section 11.5.13)

    2) ARM can generate interrupt to DSP by setting CHIPSIG 2 or CHIPSIG 3 or NMI bit of CHIPSIG Register. This corresponds to Event 5 (SYSCFG_CHIPINT2) and Event 67 (SYSCFG_CHIPINT3) of the DSP Interrupt Map (See Table 3-1 of the document). 

        I used CHIPSIG2 and configured Event 5.

    3) DSP responds to the interrupt by initiating the actions in  the ISR and clears the interrupt by writing 1 to CHIPSIG2/CHIPSIG3 bit of CHIPSIG_CLR register.

    4) Similarly, DSP can interrupt ARM by setting CHIPSIG0/1/2/3 bit of CHIPSIG Register. The corresponding events in ARM side are Event No. 28/29/30/31 (Table 12-1). 

       I selected CHIPSIG1 and so configured Event 29.

    5) ARM then clears the interrupt by writing 1 to the corresponding bit of CHIPSIG_CLR register.

    Hope, everything is clear now.

    Regards,

    Jazir

  • Where is SPRUGM7???
    There's several references on the web (TI and others) to the "OMAP-L138 Applications Processor System Reference Guide (SPRUGM7)" but I cannot locate it anywhere. TI's link says "Sorry, Can't find your page". Other sites have PDF's labeled SPRUGM7 but they are not the "OMAP-L138 Applications Processor System Reference Guide".
    I'm working on the DSP side of the OMAP-L138 now and am trying to find a good Application Reference Guide with memory map locations, etc.
    Specifically, I am looking for a reference to the ARM/DSP Shared memory block and it's Memory Mapped location on the DSP and the ARM.
    I know there's a "DSPLink " package for ARM/DSP communications but it's over-kill for my application.

  • 4061.OMAP L138 Reference guide.pdf

    Dear Terry,

    I have uploaded the SPRUGM7D document.

    Regards,

    Jazir

  • That's great. Thank you very much!