AM5728: PCIe GEN1 mode configuration

Koichiro Tashiro

Part Number: AM5728

Hi,

My customer is evaluating PCIe and found below issue.

Environment:
Software : SDK Linux ver. 06.01.00.08
Hardware: Customer board

Customer wants to use PCIe with 2lane GEN1 mode, so configure *.dts file as below.
(*.dts is changed to *.txt. Please see at line#2312 and after.)

6663.am572x-idk.txt
num-lanes = <0x2>;
max-link-speed = <0x1>;

But register values after the configuration are below:

CTRL_CORE_CONTROL_IO_2(0x4A002558)[13]=1
CTRL_CORE_PCIE_CONTROL(0x4A003C3C)[2]=1
PCIECTRL_EP_DBICS_LNK_CAP(0x5100007C)[3:0]=2 <== expected value is 1
PCIECTRL_PL_WIDTH_SPEED_CTL(0x5100080C)= 0x0002020F

Why it cannot be configured to GEN1?

Customer found below threads discussed about similar issue, but it is not clear how to solve that.
http://e2e.ti.com/support/processors/f/791/p/566421/2078367
https://e2e.ti.com/support/arm/sitara_arm/f/791/t/567936

Thanks and regards,
Koichiro Tashiro

over 5 years ago

0 Bin Liu over 5 years ago

TI__Guru**** 168631 points

Koichiro Tashiro said:
PCIECTRL_EP_DBICS_LNK_CAP(0x5100007C)[3:0]=2 <== expected value is 1

This register tell the hardware capability the PCIe controller, it doesn't change from software settings. Please read register DBICS_LNK_CAS (0x51000080) which should be 0x1 in bits 16-19.

0 Koichiro Tashiro over 5 years ago in reply to Bin Liu

TI__Mastermind 22945 points

Hi Bin,

Customer checked DBICS_LNK_CAS(0x51000080) bits 16-19 and the value is 0x1.
Does this mean the controller is configured as GEN1?
TRM does not provide any description for these bits.

Thanks and regards,
Koichiro Tashiro

0 Bin Liu over 5 years ago in reply to Koichiro Tashiro

TI__Guru**** 168631 points

Koichiro Tashiro said:
Customer checked DBICS_LNK_CAS(0x51000080) bits 16-19 and the value is 0x1.
Does this mean the controller is configured as GEN1?

Yes.

Koichiro Tashiro said:
TRM does not provide any description for these bits.

Similar to DBICS_LNK_CAP[3:0], 0x1: 2.5GT/s (Gen1), 0x2: 5GT/s (Gen2), 0x3: 8GT/s (Gen3).

0 Koichiro Tashiro over 5 years ago in reply to Bin Liu

TI__Mastermind 22945 points

Hi Bin,

Now customer understood the controller is properly configured as Gen1.
Customer wants to use Gen1 x 2lane configuration.

Could you confirm the controller is configured Gen1 x 2 lane with the dts file I attached on the first post?

Thanks and regards,
Koichiro Tashiro

0 Bin Liu over 5 years ago in reply to Koichiro Tashiro

TI__Guru**** 168631 points

Hi Koichiro-san,

The dts file (am572x-idk.txt) you provided is completely different from the one in the kernel (am572x-idk.dts), so it is hard for me to check what is changed. Please provide the dts changes in patch format for me to review.

To use PCIe in x2 lane mode, you have to configure both serdes phy to PCIe as one of them is assigned to USB1 by default, then USB1 is no longer usable since it doesn't have a serdes. There are a few e2e threads on this forum discussed how to configure to x2 lane mode, please check them out.

0 Bin Liu over 5 years ago in reply to Koichiro Tashiro

TI__Guru**** 168631 points

Hi Koichiro-san,

I was expecting a patch file for kernel source code, but I reviewed the device tree file you sent in email. I don't see the full picture because I don't have the original file to compare with, but here are my comments:

To enable x2 lane on pcie1_rc:

- add the second PCIe PHY (pcie2_phy) to pcie1_rc node, which seems already done;
- enable pcie2_phy node, which seems already done;
- disable pcie2_rc mode, because it uses pcie2_phy;
- disable omap_dwc3_1 node, because it also uses the serdes which pcir2_phy node points to.

To check if a PCIe EP is enumerated in x2 lane mode, you can check the log of command 'lspci -vv', and look for the line start with 'LnkSta:'.

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AM5728: PCIe GEN1 mode configuration