Does tda4 PCIE RC support legacy INTx

Hi Jun Li,

Legacy INTx is not supported for PCIe RC.

Regards

Dhaval Khandla

Sir:

I'm afraid I must ask for more details. The reference manual for the TDA4 specifically mentions support for legacy INTx interrupts. See the description of the PCIE_INTD_ENABLE_REG_SYS_0 register: the lower 4 bits are specifically documented to enable triggering of legacy INTx events via the PCIE_LEGACY_PULSE vector in the GIC (vector 344).

It is difficult to reconcile your blanket statement that legacy INTx interrupts are "not supported" with the amount of documentation for INTx support in the manual.

I therefore must ask for clarification. What exactly do you mean when you say "not supported?" The manual says it is. Is the manual wrong? Is the feature broken due to a silicon bug?

We know that the Linux TDA4 PCIe driver doesn't include legacy INTx support. But we're not trying to use the Linux driver: we're trying to create our own driver for the PCIe controller in the TDA4. The manual says that this feature should work, but it lacks some details about it. (Specifically, the manual doesn't make it clear just what you're supposed to write to EOI_VECTOR field in the PCIE_INTD_EOI_REG register.) We can't easily ignore INTx interrupt support because a lot of our customers have legacy PCI hardware designs which they're not prepared to discard yet.

So, please: are you certain you mean to say that the PCIe controller in the TDA4 doesn't have support for handing legacy INTx interrupts? And if so, please elaborate as to why this would be the case if the manual says it should.

-Bill

Hi Bill,

Sorry for the inadequate response.

William Paul1 said:

I therefore must ask for clarification. What exactly do you mean when you say "not supported?" The manual says it is. Is the manual wrong? Is the feature broken due to a silicon bug?

We are investigating a possible issue in silicon, and when it is confirmed either way, it will be published in the errata along with possible workarounds(if applicable). But following is the brief explanation of the issue under investigation.

PCIe End Point (EP) can signal a legacy interrupt at the PCIe Root Port (RP) by issuing a message. The message causes a level output signal at the boundary of the PCIe RP controller to go high or low. This level output signal from the controller is converted to a pulse for signaling an interrupt to the SoC interrupt controller. The EP can issue a single message and maintain the level output of the RP controller high without issuing any other message if there is pending work to be done. The End of Interrupt (EOI) feature in the interrupt logic is used to re-trigger the pulse interrupt to the SoC interrupt controller from a level signal that remains asserted. The EOI feature has not been enabled for the PCIe legacy interrupts. This results in a single pulse interrupt to be generated to the SoC interrupt controller, even if the level output signal from the PCIe RP remains asserted high. Hence, this violates the expectations of level-triggered interrupts, because it is being treated like edge-triggered interrupts.

So, this is the reason for saying that feature is not supported currently.

Regards

Dhaval Khandla