AM5728: DDR clock behaviour

Mauro Palombini

Part Number: AM5728

Dear Sirs, during DDR3 electrical signal test we found that the clock, and the other control signals as well, stop running for a short time and then restart. Is this behaviour normal? Can be caused by the idle enetering of the processor? On the attached picture C1 is the CLK, C2 is the DQS and C3 is DQ. This is repetitive untill our application starts.

Thanks a lot in advance

Mauro

over 6 years ago

0 Biser Gatchev-XID over 6 years ago

TI__Guru**** 393215 points

Hi,

What software is running on the AM572x?

0 Mauro Palombini over 6 years ago in reply to Biser Gatchev-XID

Intellectual 265 points

Hi Biser, we are running Linux 4.19 RT from SDK 6.00.01.

Best Regards

Mauro

0 JJD over 6 years ago in reply to Mauro Palombini

TI__Guru* 92350 points

Hi Mauro, it's possible that your application has enabled the DDR controller to put the DDR in Self-Refresh during periods of inactivity. Specifically, check register EMIF_POWER_MANAGEMENT_CONTROL (assuming you are using EMIF1, that is at address 0x4C000038). Set bit field LP_MODE=0 to disable the power management. See the TRM for more details on this register.

Regards,

James

0 Mauro Palombini over 6 years ago in reply to JJD

Intellectual 265 points

Dear James. Thanks for the answer. We checked the register and foud what you ppointed out but is is already on the initialization of the memory that belong on your system. By the way, thanks again for the support

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AM5728: DDR clock behaviour