Hello,
Has anyone successfully integrated the MT29C4G48MAZAPAKQ-5 IT with the OMAP3530?
I am working on SDRAM timing and have an interesting problem with respect to
the auto refresh feature, enabled in the SDRC_RFR_CTRL_0 register. Of note, this
device is 200MHz speed grade, but I am running my OMAP3530 L3 at 166MHz so
as to run this part at 166MHz.
With it on, all areas of the SDRAM produce corrupt data when writing and when reading,
and fluctuate with each clock cycle, never with a consistent pattern.
With autorefresh off, I get about a 90% success rate when working with the SDRAM - reads and
writes. The 10% failure that I get in this case I attribute to bit fade, and not properly refreshing
the rows.
I have read previous forum replies on loosening the values, but am not sure of the twelve variables
between SDRC_ACTIM_CTRLA and SDRC_ACTIM_CTRLB to start working with first. I have tried adjusting
the Twtr setting, but no success.
Can anyone help?
Thank you.