Problems With Consistent uPP Data Transmit

Hi all,

I'm having trouble transmitting a consistent stream of data over uPP from the C6748 core on the OMAPL138.

Setup Details:

C6748 is clocked at 300 MHz.
I'm utilizing the BIOS PSP 1.30.01 uPP driver.
uPP output frequency is 75 MHz (written directly to an external FIFO).
Data is read out of FIFO at 60 MHz.

I'm looking to be able to read a continuous stream of data from the FIFO, so pauses in the uPP transmit that can be buffered away are acceptable.  

My initial setup was a reworking of the PSP uPP loopback example for the OMAPL138 EVM. I whittled the example down to a thread that continuously called SIO_reclaim and SIO_issue, sending the same iterations of buffers out the uPP port. However, no matter how large I made the uPP DMA buffer, or how many buffers I used, I would see a ~100us delay between each burst sent from the uPP (each burst being the size of an individual buffer). Is the BIOS PSP uPP driver not capable of transmitting data any faster than this, or am I missing something? My channel configurations are posted below:

/* parameters for channel A (XMIT)                                                  */
Upp_ChanParams uppChanparamA =
{
    FALSE, // was TRUE, seems to have made pauses between xmit blocks smaller
    Upp_ChanSel_A,
    Upp_bitWidth_16,
    Upp_dataRate_SINGLE,
    Upp_ChanMode_NORMAL,
    Upp_dataPackFmt_RJZE,
    75000000,
    0xFFFF,
    NULL,
    NULL,
    (Upp_ErrCallback)xmitError,
    NULL,
    Upp_fifoThreshold_64,
    {
        FALSE,
        Upp_polarity_ACTIVE_HIGH,
        TRUE,
        Upp_polarity_ACTIVE_HIGH,
        TRUE,
        Upp_polarity_ACTIVE_HIGH,
        Upp_clkPol_RISING_EDGE_SYNC,
        Upp_PinIdleState_IDLE_VAL,
    }
};

void upp_my_init()
{
    Upp_init();

    uppParams = Upp_PARAMS;
    uppParams.emulationMode = Upp_EmuMode_SOFT_STOP;
    uppParams.dlbMode = Upp_Loopback_DISABLE;
    uppParams.devMode = Upp_DevMode_DUPLEX_1;
    uppParams.pscPwrmEnable = FALSE;
    uppParams.instHandlerSel = Upp_intHandlerSel_HWI;
    uppParams.pllDomain = Upp_pllDomain_0;
}

Next I removed the usage of the SIO_reclaim and SIO_issue functions, and accessed the DMA registers for the uPP directly. My code is as follows:

    while(1)
    {
        // Set the DMA address
        (*pUPID0) = (unsigned int)aLut; // contains a single period of a sin wave
        // Set the DMA line count and byte count
        (*pUPID1) = (unsigned int)(0x10000 + (unsigned int)BUFSIZE);        
        // Set the DMA line offset
        (*pUPID2) = (unsigned int)0;
        
        // Wait for DMA pend bit to be set to 0
        while((*pUPIS2)&0x2 == 0x2);
    }

This code results in a more consistent transmit pattern. BUFISZE/2 samples will be transferred, and then there will be a ~100 cycle (cycles based on 75 MHz clock coming from uPP) pause before the next transfer begins. The ~100 cycle pause is workable, and can be buffered out, however, there will occasionally be a much longer pauses (greater than 1024 cycles), that is not workable. Any insight or advice? The BIOS PSP driver routines are still being used to setup the uPP, however, afterwords I  disable uPP interrupts in hopes that the BIOS PSP functions will not be accessed. Is there something I'm missing here? My code does nothing except configure the uPP through the BIOS PSP driver, and then launch a task that runs the above code. Any insight or advice would be greatly appreciated.

Thanks in advance,
\Greg