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AM6548: DDR latency and bandwidth from R5F

Mohsen Khayami
Mastermind 22391 points
Part Number: AM6548


Hi

like to see if we have any memory bandwidth and latency numbers for the R5 (mcu island) to access the DDR on the AM654x. Also it would be good to get bandwidth and latency between the R5 and the MCU_MSRAM. We have the numbers for the A53 core but not access from the R5. We like to get these numbers as soon as possible.

Thanks

  • 0
    TI__Guru* 89485 points

    Mohsen, let me try to find out.  I don't think we have these numbers currently.

    James

  • 0 in reply to JJD
    Mastermind 7560 points

    Hi,

    I was facing the same problem, and ended up doing lots of measurements myself, see this thread:

    https://e2e.ti.com/support/processors/f/791/t/840395#pi320966=1

    One of your colleagues finally confirmed my measurements:

    yes we can confirm these latency numbers. 

    >>This leaves us with ~34 cycles for accesing MCU SRAM, ~104 cycles for accessing MSMC SRAM and ~146 cycles for accessing DDR RAM. 


    That's the latency for reading memory in R5f (400 MHz) clock cycles. Bandwidth is highly dependent on how you access the data, e.g. cached/uncached, and also if you're reading or writing. I fiddled around with prefetching and was able to hide some of the latency, but at 146 cycles the core is bound to spend a lot of time waiting.

    If you have more specific questions feel free to ask, maybe it's something we've already encountered.

    Regards,

    Dominic

  • 0 in reply to Dominic Rath
    Mastermind 7560 points

    For unrelated reasons (questions about cache coherency) I re-used my R5f test programs on the A53, and noticed rather high latencies when accessing MSMC SRAM from the A53. An uncached (memory attribute index 4) 64-bit read from MSMC SRAM takes ~56 cycles, or ~70ns (at 800 MHz). This is still way better than an access from the R5f, but almost twice the latency listed in AM65xx System Performance (SPRACI6).

    : You wrote that you have numbers for the A53 core - are you refering to SPRACI6, e.g. 40ns for accesses to MSMC? Have you verified these numbers?