McBSP Driver issues

Hi Jeremiah,

McBSP can be configured by opening the McBSP driver in different modes, like, for receive use SIO_INPUT and for transmit use the SIO_OUTPUT while creating the device by calling SIO_Create().

Note: For more details on channel creation visit section 3.3.3 of McBSP dirver design document

To have both Receive and Transmit, the SIO_create() needs to be called first for transmit and then for receive.

The sequence for transmit would be,

     SIO_create() in SIO_INPUT mode

     SIO_issue() for priming the buffers

     Combination of SIO_reclaim() and SIO_issue() for ‘n’ number of times.

     SIO_close()

The sequence for receive would be,

      SIO_create() in SIO_OUTPUT mode

      SIO_issue() for priming the buffers

      Combination of SIO_reclaim() and SIO_issue() for ‘n’ number of times.

      SIO_close()

The change in the configuration for transmit would be (in the sample application),

Mcbsp_DataConfig mcbspChanConfig =

{

    Mcbsp_Phase_SINGLE,

    Mcbsp_WordLength_8,

    Mcbsp_WordLength_8,    

    NUM_OF_CHANNELS,

    NUM_OF_CHANNELS,       

    Mcbsp_FrmSync_DETECT,

    Mcbsp_DataDelay_1_BIT,

    Mcbsp_Compand_OFF_MSB_FIRST,

    Mcbsp_BitReversal_DISABLE,

    Mcbsp_IntMode_ON_SYNCERR,

    Mcbsp_RxJust_RZF,                                    /* Dont care for TX         */

    Mcbsp_DxEna_OFF                      /* Replace with Mcbsp_DxEna_ON for Transmit */

};

Note: As mentioned in the McBSP dirver design document “BIOSPSP_McBSP_Driver_Design.pdf”, section 3.5.6.

For more details refer BIOSPSP_McBSP_Driver_Design document and also the user guide. 

Thanks and Regards,

Sandeep K

Thank you for your help. However, the above information did not assist me in getting the problem fixed. What ended up being the root of my problem was asked in the last sentence of my original post:

What is the proper channel/device configuration to get the slave to transmit in a four wire mode?

In order to get the Mcbsp slave working in four channel mode, FSX becomes an input pin and must be tied ti FSR. Similarly CLKX becomes an input and must be tied to CLKR. Once I realized this, I was able to get the McBSP slave to both receive and transmit.

The only thing I am noticing is that the slave starts transmitting one frame after it starts receiving. Is there anyway to make it so that the receive and transmit start on the same frame? Thanks.

Hi Jeremiah,

Sincere apologies for the delayed response.

Since you have made the transmit FSX and CLKX as the input and the FS & CLK signals for transmit are derived from the receive (i.e FSR and CLKR). So whenever receive generated the FS, the transmit get the FS signal and then only it transmission. This could be the reason why you are observing the delay in slave transmit.

What I can suggest you is to use the following configuration for slave transmit,

/* Clock setup TX section */
Mcbsp_ClkSetup mcbspClkConfig =
{
    Mcbsp_FsClkMode_DXR_XSR,  /*was Mcbsp_FsClkMode_EXTERNAL,*/
    ......

 };

This will generate the FS signal on the completion of DXR to XSR copy, and this may solve the delayed response of the transmit slave.

Note: With the above option enabled, the data delay should be configured to "Mcbsp_DataDelay_1_BIT". Also please make sure that the open the transmit first and then the receive.

Let me know the result.

Could you please share both the receive and transmit slave configurations?

I guess, you are using the BIOS PSP version 1.30.01.

Thanks and Regards,

Sandeep K 
 

By changing the FsClk mode as suggested, the slave no longer transmits.

Here is my configuration.

Mcbsp_DataConfig Mcbsp1TXChanConfig =

{

Mcbsp_Phase_SINGLE,

Mcbsp_WordLength_32,

/* Dont care */

NUM_OF_CHANNELS,

/* Dont care */

/* Dont care for TX */

/* Dont care */

/* Dont care */

/* Dont care for TX */

/* 96KHz ????? */

/* 96KHz ????? */

{

Mcbsp_WordLength_32,

/* wordlength configured */

/* user loopjob length */

/* EDMA event queue */

/* hwi number */

/* FIFO mode enabled */

* channel configuration */

/* clock configuration */

/* multi channel control */

//Channel enable mask for X/RCERE0

//Channel enable mask for X/RCERE1 40-47

//Channel enable mask for X/RCERE2

//Channel enable mask for X/RCERE3

{

Mcbsp_WordLength_32,

/* wordlength configured */

/* user loopjob length */

/* EDMA event queue */

/* hwi number */

/* FIFO mode enabled */

/* channel configuration */

/* clock configuration */

/* multi channel control */

//Channel enable mask for X/RCERE0

//Channel enable mask for X/RCERE1 40-47

//Channel enable mask for X/RCERE2

//Channel enable mask for X/RCERE3

Please note, that due to bug SDOCM00077966 the input stream has to be confirued before the output stream.