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Unreliable Ethernet comms

I've been battling with the DM648 + Marvell 88E1111 PHY, as used on the Lyretech EVM, on our own board. I can't get reliable comms over the Ethernet port. Sometimes it will ping for 15 minutes (using an auto-ping program) then stop responding, sometimes coming back again after a few minutes. Using the TI supplied speed test package usually results in an instantaneous crash. Occasionally it will stagger along at a few tens of kb/s, compared the the EVM which runs at 80Mb/s or so with exactly the same software running in the DM648.

I've been all round the PHY cleaning up power supplies, even driving an external precision signal generator into the 25MHz clock input instead of the crystal. Nothing has made any difference to the Ethernet comms reliability. The system always crashes within seconds of starting the speed test program, usually before even indicating a speed result. The signals out to the RJ45 are short, differential, controlled impedance. The board always achieves a 1Gb/s link to a laptop which would seem to indicate that the RJ45 side of things is ok. The MDI is also ok since we can get status and ID back from the PHY. The problem seems to be when data is sent to the TCP/IP stack over the SGMII.

The SGMII connections to the DM648 are about 30mm, differential, controlled impedance. This is much shorter than on the Lyretech EVM which runs the SGMII across half the board, via SMA connectors and then into the PHY. We've disabled the unused SGMII1 as we 're only using one PHY on SGMII0.

The only area I've not been able to change is the SGMII since it's buried in an internal layer. There is a register in the PHY to set the loading impedance on the SGMII but the TI driver doesn't give access to this register.

Meantime I've had to abandon the Ethernet port and use the UART to connect the DM648 to the rest of the system, which is not ideal but seems to work, having changed the main clock crystal to generate an accurate baud rate.

Any ideas most welcome!

Bill

  • I am checking with DM648 ethernet expert. I will get back to you as soon as I get his comments.

    Regards, Srirami.

  • Bill,

    Did you make that your design is compliant with the "Table 6-81. Ethernet Subsystem Timing Requirements" in DM648 data sheet (Page 163)?

    Also did you check that REFCLKP/N pins are AC coupled as per the Foot Note on Page 20 in DM648 Data sheet?

    Regards, Srirami.

  • Bill,

    Do you need any example code to modify the PHY registers ? 

    Regards

    Varada

  • Hi Srirami,

    Many thanks for getting back to me on this problem. Yes, the REFCLK P/N pins are ac coupled. I used the Lyretech EVM as the reference design for our board, using exactly the same (Marvell 88E1111) PHY.

    Bill

     

     

  • Varada,

    Many thanks for replying. Yes please. In particular I'd like to be able to adjust PHY registers 29 and 30, page 18. These registers will let me experiment with the impedance matching between the DM648 and the PHY on the SGMII.

    Thanks,

    Bill

  • Bill - the code I have got was built for initial device verification. 

     

    Here is the simple PHY read/write routines and a simple function to program it in loopback mode. Hope you can leverage this to build a small app to modify PHY registers.

    Please let me know if you need further help and outcome.

     

    All the Best.

    Regards

    Varada

    ---------------------------------------------------------------------------------

    #define PHYREG_read(regadr, phyadr)                             \

                MDIO_REGS->USERACCESS0 =                            \

                        CSL_FMK(MDIO_USERACCESS0_GO,1u)         |   \

                        CSL_FMK(MDIO_USERACCESS0_REGADR,regadr) |   \

                        CSL_FMK(MDIO_USERACCESS0_PHYADR,phyadr)



    #define PHYREG_write(regadr, phyadr, data)                      \

                MDIO_REGS->USERACCESS0 =                            \

                        CSL_FMK(MDIO_USERACCESS0_GO,1u)         |   \

                        CSL_FMK(MDIO_USERACCESS0_WRITE,1)       |   \

                        CSL_FMK(MDIO_USERACCESS0_REGADR,regadr) |   \

                        CSL_FMK(MDIO_USERACCESS0_PHYADR,phyadr) |   \

                        CSL_FMK(MDIO_USERACCESS0_DATA, data)


    #define PHYREG_wait()                                           \

                while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) )


    #define PHYREG_waitResults( results )                       \

                while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) );             \

                results = CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_DATA)


    ---------------------------------------------------------------------------------

     

    void Configure_PHYLoopback(void)

    {

    unsigned int temp=0;

     

    *(volatile unsigned int*)(0x02d04004) =0x410000FF; // Enable MDIO State machine

    //As per Marvell PHY Specification configuring PHY Loopback


    for(temp=0;temp<4000;temp++)

    {

    asm(" NOP ");

    }

     

    PHYREG_write(0x16,0x01,0x01);

    PHYREG_wait();

    PHYREG_write(0x00,0x01,0x8140);

    PHYREG_wait();

    PHYREG_write(0x00,0x01,0x4140);

    PHYREG_wait();

     

    }

     

  • Also attaching the include files for CSL macros.

    3733.cslr_cpsw.zip