Changing DSPLink default memory map

    
Entered RDWR_Create ()                                                         
[  128.977783] Error: DSP-side memory map does not match configuration.        
[  128.977813] Compare DSP-side TCF/MAP file with /dsplink/config/all/CFG_<PLATF
ORM>.c                                                                         
PROC_load failed. Status: [0x80008013]                                         
Leaving RDWR_Create ()                                                         
Create phase failed. Status: [0x80008013]                                      
Entered RDWR_Delete ()                                                         
Assertion failed (IS_VALID_MSGQ (msgqQueue)). File : msgq.c Line : 484         
MSGQ_release () failed. Status = [0x8000800b]                                  
MSGQ_transportClose () failed. Status = [0x80008000]                           
Leaving RDWR_Delete ()   

Here are the changes I made in CFG_OMAP3530_SHMEM.c    (only the beginning of the file, the rest left unchanged):

/** ============================================================================
 *  @file   CFG_OMAP3530_SHMEM.c
 *
 *  @path   $(DSPLINK)/config/all/
 *
 *  @desc   Defines the configuration information for DSP/BIOS LINK for the
 *          OMAP platform.
 *
 *  @ver    1.61.03
 *  ============================================================================
 *  Copyright (c) Texas Instruments Incorporated 2002-2008
 *
 *  Use of this software is controlled by the terms and conditions found in the
 *  license agreement under which this software has been supplied or provided.
 *  ============================================================================
 */


/*  ----------------------------------- DSP/BIOS LINK Headers       */
#include <dsplink.h>
#include <procdefs.h>


#if defined (__cplusplus)
EXTERN "C" {
#endif /* defined (__cplusplus) */

/** ============================================================================
 *                                DSPLINK MEMORY SECTION DIAGRAM
 *
 *         |--------------[ 0xXXXXXX00 ]---------------------------------|
 *         |                                                             |
 *         |                   RESET VECTOR (0x80)                       |
 *         |               Last two nibbles must be zero                 |
 *         |                                                             |
 *         |-------------------------------------------------------------|
 *         |                                                             |
 *         |                   DSP CODE/DATA                             |
 *         |               DSP executable is loaded to this section      |
 *         |                                                             |
 *         |=============================================================|
 *         |                                                             |
 *         |                   DSPLINK SHARED MEMORY0                    |
 *         |               Shared control structure is loaded here       |
 *         |                                                             |
 *         |-------------------------------------------------------------|
 *         |                                                             |
 *         |                   DSPLINK SHARED MEMORY1                    |
 *         |               Shared control structure is loaded here       |
 *         |                                                             |
 *         |-------------------------------------------------------------|
 *         |                                                             |
 *         |                   POOL Buffer Memory                        |
 *         |               Pool's buffers are created in this area       |
 *         |                                                             |
 *         |-------------------------------------------------------------|
 *
 *  ============================================================================
 */

/** ============================================================================
 *  @name   DRVHANDSHAKEPOLLCOUNT
 *
 *  @desc   POLL Count for Driver handshake.
 *  ============================================================================
 */
#define  DRVHANDSHAKEPOLLCOUNT        ((Uint32) 0xFFFFFFFu)

/** ============================================================================
 *  @name   RESETCTRLADDR
 *
 *  @desc   Indicates the start address of Reset Ctrl memory region.
 *          last two nibbles must be zero i.e. align to 256 boundary.
 *  ============================================================================
 */
#define  RSTENTRYID         0u
#define  RESETCTRLADDR      0x87E00000u
#define  RESETCTRLSIZE      0x80u

/** ============================================================================
 *  @name   CODEMEMORYADDR/CODEMEMORYSIZE
 *
 *  @desc   Indicates startaddress/size for dsplink code region.
 *  ============================================================================
 */
#define  CODEENTRYID        1u
#define  CODEMEMORYADDR     (RESETCTRLADDR + RESETCTRLSIZE)
#define  CODEMEMORYSIZE     0x1aFFF80u

/** ============================================================================
 *  @name   SHAREDENTRYID/SHAREDMEMORYADDR/SHAREDMEMORYSIZE
 *
 *  @desc   Indicates startaddress/size for dsplink shared memory region.
 *  ============================================================================
 */
#define  SHAREDENTRYID0     2u
#define  SHAREDMEMORYADDR0  (CODEMEMORYADDR + CODEMEMORYSIZE)
#define  SHAREDMEMORYSIZE0  0x5000u

/** ============================================================================
 *  @name   SHAREDENTRYID/SHAREDMEMORYADDR/SHAREDMEMORYSIZE
 *
 *  @desc   Indicates startaddress/size for dsplink shared memory region.
 *  ============================================================================
 */
#define  SHAREDENTRYID1     3u
#define  SHAREDMEMORYADDR1  (SHAREDMEMORYADDR0 + SHAREDMEMORYSIZE0)
#define  SHAREDMEMORYSIZE1  0x2B000u

/** ============================================================================
 *  @name   POOLMEMORYADDR/POOLMEMORYSIZE
 *
 *  @desc   Indicates startaddress/size for dsplink POOL memory region.
 *  ============================================================================
 */
#define  POOLENTRYID        4u
#define  POOLMEMORYADDR     (SHAREDMEMORYADDR1 + SHAREDMEMORYSIZE1)
#define  POOLMEMORYSIZE     0x004D0000u

/** ============================================================================
 *  @name   LINKCFG_memTable_00
 *
 *  @desc   Memory table ID 0.
 *  ============================================================================
 */
STATIC LINKCFG_MemEntry  LINKCFG_memTable_00 [] =
{
    {
        RSTENTRYID,                        /* ENTRY          : Entry number */
        "RESETCTRL",                       /* NAME           : Name of the memory region */
        RESETCTRLADDR,                     /* ADDRPHYS       : Physical address */
        RESETCTRLADDR,                     /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1u,                      /* ADDRGPPVIRT    : GPP virtual address (if known) */
        RESETCTRLSIZE,                     /* SIZE           : Size of the memory region */
        TRUE,                              /* SHARED         : Shared access memory? */
        FALSE,                             /* SYNCD          : Synchornized? */
    },
    {
        CODEENTRYID,                       /* ENTRY          : Entry number */
        "DDR2",                            /* NAME           : Name of the memory region */
        CODEMEMORYADDR,                    /* ADDRPHYS       : Physical address */
        CODEMEMORYADDR,                    /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1u,                      /* ADDRGPPVIRT    : GPP virtual address (if known) */
        CODEMEMORYSIZE,                    /* SIZE           : Size of the memory region */
        TRUE,                              /* SHARED         : Shared access memory? */
        FALSE,                             /* SYNCD          : Synchornized? */
    },
    {
        SHAREDENTRYID0,                   /* ENTRY          : Entry number */
        "DSPLINKMEM",                     /* NAME           : Name of the memory region */
        SHAREDMEMORYADDR0,                /* ADDRPHYS       : Physical address */
        SHAREDMEMORYADDR0,                /* ADDRDSPVIRT    : DSP virtual address */
       (Uint32) -1u,                      /* ADDRGPPVIRT    : GPP virtual address (if known) */
        SHAREDMEMORYSIZE0,                /* SIZE           : Size of the memory region */
        TRUE,                             /* SHARED         : Shared access memory? */
        FALSE,                            /* SYNCD          : Synchornized? */
    },
    {
        SHAREDENTRYID1,                   /* ENTRY          : Entry number */
        "DSPLINKMEM1",                    /* NAME           : Name of the memory region */
        SHAREDMEMORYADDR1,                /* ADDRPHYS       : Physical address */
        SHAREDMEMORYADDR1,                /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1u,                     /* ADDRGPPVIRT    : GPP virtual address (if known) */
        SHAREDMEMORYSIZE1,                /* SIZE           : Size of the memory region */
        TRUE,                             /* SHARED         : Shared access memory? */
        FALSE,                            /* SYNCD          : Synchornized? */
    },
    {
        POOLENTRYID,                       /* ENTRY          : Entry number */
        "POOLMEM",                         /* NAME           : Name of the memory region */
        POOLMEMORYADDR,                    /* ADDRPHYS       : Physical address */
        POOLMEMORYADDR,                    /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1u,                      /* ADDRGPPVIRT    : GPP virtual address (if known) */
        POOLMEMORYSIZE,                    /* SIZE           : Size of the memory region */
        TRUE,                              /* SHARED         : Shared access memory? Logically */
        FALSE,                             /* SYNCD          : Synchornized? */
    },
    {
        5,                     /* ENTRY          : Entry number */
        "DSPIRAM",             /* NAME           : Name of the memory region */
        0x5c7f8000,            /* ADDRPHYS       : Physical address */
        0x107f8000,            /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0x00018000,            /* SIZE           : Size of the memory region */
        TRUE,                  /* SHARED         : Shared access memory? */
        FALSE                  /* SYNCD          : Synchornized? */
    },
    {
        6,                     /* ENTRY          : Entry number */
        "DSPL1PRAM",           /* NAME           : Name of the memory region */
        0x5cE00000,            /* ADDRPHYS       : Physical address */
        0x10E00000,            /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0x00008000,            /* SIZE           : Size of the memory region */
        TRUE,                  /* SHARED         : Shared access memory? */
        FALSE                  /* SYNCD          : Synchornized? */
    },
    {
        7,                     /* ENTRY          : Entry number */
        "DSPL1DRAM",           /* NAME           : Name of the memory region */
        0x5cF04000,            /* ADDRPHYS       : Physical address */
        0x10F04000,            /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0x00014000,            /* SIZE           : Size of the memory region */
        TRUE,                  /* SHARED         : Shared access memory? */
        FALSE                  /* SYNCD          : Synchornized? */
    },
    {
        8,                     /* ENTRY          : Entry number */
        "L4_CORE",             /* NAME           : Name of the memory region */
        0x48000000,            /* ADDRPHYS       : Physical address */
        0x48000000,            /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0x01000000,            /* SIZE           : Size of the memory region */
        FALSE,                 /* SHARED         : Shared access memory? */
        FALSE                  /* SYNCD          : Synchornized? */
    },
    {
        9,                     /* ENTRY          : Entry number */
        "L4_PER",              /* NAME           : Name of the memory region */
        0x49000000,            /* ADDRPHYS       : Physical address */
        0x49000000,            /* ADDRDSPVIRT    : DSP virtual address */
        (Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
        0x00100000,            /* SIZE           : Size of the memory region */
        FALSE,                 /* SHARED         : Shared access memory? */
        FALSE                  /* SYNCD          : Synchornized? */
    }
} ;

Here are the changesi made in dsplink-omap3530-base.tci :

/** ============================================================================
 *  @file   dsplink-omap3530-base.tci
 *
 *  @path   $(DSPLINK)/dsp/inc/DspBios/5.XX/OMAP3530/
 *
 *  @desc   This file defines base configuration for DSP/BIOS LINK.
 *
 *  @ver    1.61.03
 *  ============================================================================
 *  Copyright (c) Texas Instruments Incorporated 2002-2008
 *
 *  Use of this software is controlled by the terms and conditions found in the
 *  license agreement under which this software has been supplied or provided.
 *  ============================================================================
 */

/*  ============================================================================
 *  Load assert support
 *  ============================================================================
 */
utils.importFile("assert.tci");

/*  ============================================================================
 *  Load base TCI file.
 *  ============================================================================
 */
utils.loadPlatform("ti.platforms.evm3530");

/*  ============================================================================
 *  Enable common BIOS features used by all examples
 *  ============================================================================
 */
bios.disableRealTimeAnalysis(prog);
bios.enableMemoryHeaps(prog);
bios.disableRtdx(prog);
bios.enableTskManager(prog);

/*  ============================================================================
 *  GBL
 *  Enable 32K of L2 cache, 32K of L1D cache and 16K for L1P.
 *  Adjust the size of IRAM, L1DSRAM, L1PSRAM accordingly.
 *  Enable caching for addresses 0x8700_0000 - 0x87FF_FFFF by setting MAR135
 *  ============================================================================
 */
prog.module("GBL").ENABLEALLTRC        = false ;
prog.module("GBL").PROCID              = parseInt (arguments [0]) ;


prog.module("GBL").C64PLUSCONFIGURE    = true  ;
prog.module("GBL").C64PLUSL2CFG        = "32k" ;
prog.module("GBL").C64PLUSL1DCFG       = "32k" ;
prog.module("GBL").C64PLUSL1PCFG       = "16k";
prog.module("GBL").C64PLUSMAR128to159  = 0x00000380 ;

var IRAM = prog.module("MEM").instance("IRAM");
IRAM.len              = IRAM.len - 0x8000;

var L1DSRAM = prog.module("MEM").instance("L1DSRAM");
L1DSRAM.len           = L1DSRAM.len - 0x8000;

/* Was defined for sdp3430, but not for evm3530, hence commented
var L1PSRAM = prog.module("MEM").instance("L1PSRAM");
L1PSRAM.len           = L1PSRAM.len - 0x4000;
*/

/*  ============================================================================
 *  MEM
 *  ============================================================================
 */
prog.module("MEM").STACKSIZE = 0x1000 ;

/*  ============================================================================
 *  MEM : RESET_VECTOR
 *  ============================================================================
*/
var RESET_VECTOR = prog.module("MEM").create("RESET_VECTOR");
RESET_VECTOR.base        = 0x87E00000 ;
RESET_VECTOR.len         = 0x00000080;
RESET_VECTOR.space       = "code/data";
RESET_VECTOR.createHeap  = false;
RESET_VECTOR.comment     = "RESET_VECTOR";

/*  ============================================================================
 *  MEM : Adjust DDR2
 *  ============================================================================
*/
var DDR2 = prog.module("MEM").instance("DDR2");
DDR2.base             = RESET_VECTOR.base + RESET_VECTOR.len ;
DDR2.len              = 0x01aFFF80;
DDR2.space            = "code/data";
DDR2.createHeap       = true;
DDR2.heapSize         = 0x1000000;
DDR2.comment          = "DDR2";

/*  ============================================================================
 *  MEM : DSPLINKMEM
 *  ============================================================================
 */
var DSPLINKMEM = prog.module("MEM").create("DSPLINKMEM");
DSPLINKMEM.base             = DDR2.base + DDR2.len ;
DSPLINKMEM.len              = 0x00030000;
DSPLINKMEM.createHeap       = false;
DSPLINKMEM.comment          = "DSPLINKMEM";

/*  ============================================================================
 *  MEM : DSPLINKMEM
 *  ============================================================================
 */
var POOLMEM = prog.module("MEM").create("POOLMEM");
POOLMEM.base             = DSPLINKMEM.base + DSPLINKMEM.len ;
POOLMEM.len              = 0x4D0000;
POOLMEM.createHeap       = false;
POOLMEM.comment          = "POOLMEM";

Can anyone tell me what's wrong?

Thanks

Yony