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The problem with EDMA3 link-to-self transfer in C6747

Lian
Intellectual 370 points

Now I use MCASP1 to receive data with EDMA3.  It has succeeded when set the EDMA3 LINK  to  null (the value of LINK is FFFFh). As is shown in the following picture, the received data is 0xFFFFFFFF,0xFFFFFFFF,0x00000001,0x00000002,0x00000003,......,0x00000062 in turn,  the received data numbers are 100*32bits in all.

After it received the data for the first time, it can't receive the data for the second time because its ACNT and BCNT are both 0. However, I  hope the EDMA3 can autoinitialize, so I set the EDMA3 LINK to "parameter set 127". And  set  the LINK of "the parameter set 127" to itself.  Now it can receive data for many times, but the received data is wrong. And the received data is changed every time.  

Please give me some suggestion! Thanks a lot! O(∩_∩)O~

My code is ,

 

edma3ccRegs->PARAMSET[127].OPT = (CSL_EDMA3CC_OPT_TCINTEN_ENABLE << CSL_EDMA3CC_OPT_TCINTEN_SHIFT)|\

                    (0x02 << CSL_EDMA3CC_OPT_TCC_SHIFT)|\

                     (CSL_EDMA3CC_OPT_SYNCDIM_ASYNC << CSL_EDMA3CC_OPT_SYNCDIM_SHIFT);

edma3ccRegs->PARAMSET[127].SRC = 0x01D06000;

edma3ccRegs->PARAMSET[127].A_B_CNT = (Uint32) 0x00640004;

edma3ccRegs->PARAMSET[127].DST = (Uint32) &rcv;

edma3ccRegs->PARAMSET[127].SRC_DST_BIDX = (0x0004 << CSL_EDMA3CC_SRC_DST_BIDX_DSTBIDX_SHIFT)|\

                             (0x0000 << CSL_EDMA3CC_SRC_DST_BIDX_SRCBIDX_SHIFT);

edma3ccRegs->PARAMSET[127].LINK_BCNTRLD = 0x00644FE0;

edma3ccRegs->PARAMSET[127].SRC_DST_CIDX = (Uint32)0x00;

edma3ccRegs->PARAMSET[127].CCNT = (Uint32)0x01;

 

edma3ccRegs->EMCR = (Uint32) 0x0004;

edma3ccRegs->SECR = (Uint32) 0x0004;

edma3ccRegs->DRA[1].DRAE = (Uint32) 0x000C;

edma3ccRegs->EESR = (Uint32) 0x0004;

edma3ccRegs->DMAQNUM[0] = (CSL_EDMA3CC_DMAQNUM_E2_Q0 << CSL_EDMA3CC_DMAQNUM_E0_SHIFT);

edma3ccRegs->PARAMSET[2].OPT = (CSL_EDMA3CC_OPT_TCINTEN_ENABLE << CSL_EDMA3CC_OPT_TCINTEN_SHIFT)|\

                                 (0x02 << CSL_EDMA3CC_OPT_TCC_SHIFT)|\

                                 (CSL_EDMA3CC_OPT_SYNCDIM_ASYNC << CSL_EDMA3CC_OPT_SYNCDIM_SHIFT);

edma3ccRegs->PARAMSET[2].SRC = 0x01D06000;

edma3ccRegs->PARAMSET[2].A_B_CNT = (Uint32) 0x00640004;

edma3ccRegs->PARAMSET[2].DST = (Uint32) &rcv;

edma3ccRegs->PARAMSET[2].SRC_DST_BIDX = (0x0004 << CSL_EDMA3CC_SRC_DST_BIDX_DSTBIDX_SHIFT)|\

                                  (0x0000 << CSL_EDMA3CC_SRC_DST_BIDX_SRCBIDX_SHIFT);

edma3ccRegs->PARAMSET[2].LINK_BCNTRLD = 0x00644FE0;

edma3ccRegs->PARAMSET[2].SRC_DST_CIDX = (Uint32)0x00;

edma3ccRegs->PARAMSET[2].CCNT = (Uint32)0x01;