PROCESSOR-SDK-AM335X: GMPC configuration

Hi Gaurav,

When interfaced with a NAND memory GPMC does not use the memory mapped addressing to access different addresses within the NAND memory. Instead the NAND software driver writes to GPMC_NAND_ADDRESS_i during the address phase to tell the NAND memory which address to access.

I think the only bit in GPMC_CONFIG7 that you need to specify is the CSVALID bit:
CSVALID:
Chip-select enable (reset value is 1 for CS[0] (active low) and 0 for CS[1] to CS[5] (active low)).
0h (R/W) = CS (active low) disabled
1h (R/W) = CS (active low) enabled

The MASKADDRESS and BASEADDRESS bits in GPMC_CONFIG7 should only apply to non-NAND accesses where memory mapped accesses are translated to GPMC address bit values.

Let us know if you need any other help with the GPMC configuration registers.

Hope this helps,
Mark

Hi Mark,

Thanks for your answer. 

I need some help to configure timing parameters.

I am using MT29F8G08ABACAH4-ITC TR NAND Flash. 

Thanks for your support.

Regards,

Gaurav

Hi Mark,

I am eagerly waiting for your answer.

Regards

Gaurav

Hi Gaurav,

I think the easiest way to learn about the GPMC_CONFIG registers is to study what has worked for other NAND devices and then to adapt the register bit fields to work with your NAND.

Are you using Device Tree to configure the NAND? Will you be booting from the NAND?

=-=-=-=-
Understand what the GPMC_CONFIG registers do for NAND during each phase of a NAND access
Refer to the AM335x TRM: www.ti.com/.../spruh73
* 7.1.2.3.12.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
* 7.1.2.3.12.1.2 NAND Device Command and Address Phase Control
* 7.1.2.3.12.1.3 Command Latch Cycle
  - nCE is controlled by the CSONTIME and CSWROFFTIME timing parameters.
  - CLE is controlled by the ADVONTIME and ADVWROFFTIME timing parameters.
  - nWE is controlled by the WEONTIME and WEOFFTIME timing parameters.
  - ALE and nRE (nOE) are maintained inactive.
* 7.1.2.3.12.1.4 Address Latch Cycle
  - nCS is controlled by the CSONTIME and CSWROFFTIME timing parameters.
  - ALE is controlled by the ADVONTIME and ADVWROFFTIME timing parameters.
  - nWE is controlled by the WEONTIME and WEOFFTIME timing parameters.
  - CLE and nRE (nOE) are maintained inactive.
* 7.1.2.3.12.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
  - nCS is controlled by the CSONTIME and CSRDOFFTIME timing parameters.
  - nRE is controlled by the OEONTIME and OEOFFTIME timing parameters.
* 7.1.2.3.12.1.6 NAND Device General Chip-Select Timing Control Requirement
7.1.2.3.12.1.7 Read and Write Access Size Adaptation
7.1.2.3.12.1.7.1 8-Bit Wide NAND Device

=-=-=-=-
Study existing device trees and documentation for NAND on AM335x...

* github.com/.../am335x-evm.dts
* github.com/.../omap-gpmc.txt
* e2e.ti.com/.../492193
* e2e.ti.com/.../343017

=-=-=-=-
Study the NAND driver

* In Processor SDK... processor-sdk-linux/drivers/mtd/nand/raw/omap2.c
* processors.wiki.ti.com/.../AM335x_NAND_Driver's_Guide
* software-dl.ti.com/.../NAND.html

Hope this helps,
Mark

Mark,

I will look into your suggestions then I'll let you know.

Yes, I will boot the device from NAND.

Regards

Gaurav

Hi Mark,

Most of the threads are based on linux and I am using Windows host PC.

Anyway, I have one confusion that in our NAND memory device, different commands take different address cycles and for some operations it takes command-address-command-data then how can I configure timings for different operations?

Do I need to configure timings for minimum cycles or maximum cycles?

Regards,

Gaurav

Hi Gaurav,

Since the NAND accesses are entirely software managed (not memory mapped addressing), you can tweak the timings in the CONFIG registers depending on the command or the sequence of command/address cycles.

Or you can probably configure once for the slowest access if it still satisfies the rest of the timings.

Regards,
Mark

Hi Mark,

Thanks for your reply.

Is it necessary to configure timing parameters? If wait pin is available so can I monitor this wait pin instead of timing parameters configuration. Is it right?

Because we are not doing any memory mapping for this NAND. Just we have to send the byte address through Address Register and we can monitor the wait pin. 

Please let me know whether it is right way or wrong?

Regards,

Gaurav