ISR of CHIPSIGINT2 invoked 2 times on OMAP-L138

William Young said:

When I writting a  linux kernel module to implement ARM/DSP communication, use CHIPSIG2 in SYSCFG.CHIPSIG.

I found a strange problem that my ISR of CHIPSIGINT2 got invoked 2 times though I only write a 1 to CHIPSIG.BIT[2] just once.

Here is my codes:

1. The registration of IRQ:

request_irq(irq, IRGF_RISING, dsplink_isr, "MyDSPLINK", NULL);//  CHIPSIGINT2, irq=30 as in SPRUGM7D

I though maybe the irq flag is wrong, So I changed IRQF_RISING for FALLING or even 0, but that makes no difference.

2. Interrupt Service Routine:

dsplink_isr(int irq, void *dev_id)

{

   ......

 iowrite32(1 << 2, remapped_chipsig_clr); // clear the CHIPSIGINT2 interrupt status

 iowrite32(irq, remapped_aintc_sicr); // clear interrupt in ARM interrupt controller.

// or iowrite32(1 << irq, remapped_aintc_secr1); // maybe do the same thing as above.

printk("<1>ISR invoked.\n"); 

......

}

But always the ISR run 2 times.And if i didn't clear CHIPSIGINT2 interrupt in AINTC,the ISR will run 3 times!

I searched the BBS,and found somebody got same problem on OMAP-L137.

Could somebody point out how can I fix this problem.

PS: After ISR invoked,I checked /proc/interrupts and it appears that there is only 1 interrupt occurs, but ISR runs 2 times!

Thank you!

-- William

When I provide the IRQF_DISBLED to request_irq(),the problem resovled.

Though you still have to set SECR1 (or SICR) after clear CHIPSIGINT2 in SYSCFG0,

then do other stuff you want in ISR.

This post will be helpful:

http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/77657/278106.aspx#278106

Thank you!