I would like to summarize my sample app before I get to explaining the issue I am facing:
I have an algorithm handle, with memory allocated in DDR2, that I am passing over various cores on the C6472 for some distributed processing. I am using SMMQT for passing the handle (pointer only) from core to core. Since each core modifies the handle memory I do BCACHE_wbInv(<handle pointer>) before MSGQ_put() on that core, to maintain cache coherence.
I am using mqtciv_1_20. When I used the pre-built SMMQT drivers I could work fine (with some minor workarounds). Now that I want to place the SMMQT shared buffers in DDR2, I have recompiled the drivers with _CACHELINE_SIZE defined to 128 (L2 cacheline size; pre-bulilt drivers set it to 64). But with the newly built drivers the handle memory seems corrupted on remote cores.
I am unable to understand how SMMQT is affecting cache operations on completely unrelated memory (in this case the alg handle). I can see in the release notes of mqtciv_1_20 "SDSCM00026206: Cache Bug in SMMQT Driver" resolved.
Can anybody throw any light on this?