Part Number: AM5K2E04
Dear all,
we have designed and manufactured an AM5K2E04 based board which uses both PCI Express controllers of the Keystone II and all in all, everything is working nicely.
One of the boards however shows a PCI express initialiazation problem: The PCIe link (2 lanes) between the Keystone II and the connected PCIe end-point device cannot be established and the DEBUG0 register of the PCIe controller shows.
LTSSM = 0x03 = POLL_COMPLIANCE
The PCIe specification states, that this state be only entered, when the PCIe device is deliberately put into test mode. However, we do not do this so it must be some kind of Keystone-proprietary behaviour. The effect is only observed on one out of many boards and only when the board is in a certain temperature range. So it's most likely either a production defect or bug in the physical design of the board.
My questions are:
- Does anyone have a hint how/where to (physically/electrically) investigate further?
- What could lead a Keystone II to enter POLL_COMPLIANCE state if test mode is NOT activated?
Cheers,
Gerald