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AM5K2E04: PCI Express controller reports test state "POLL COMPLIANCE". How could this happen?

Part Number: AM5K2E04

Dear all,

we have designed and manufactured an AM5K2E04 based board which uses both PCI Express controllers of the Keystone II and all in all, everything is working nicely.

One of the boards however shows a PCI express initialiazation problem: The PCIe link (2 lanes) between the Keystone II and the connected PCIe end-point device cannot be established and the DEBUG0 register of the PCIe controller shows.

LTSSM = 0x03 = POLL_COMPLIANCE

The PCIe specification states, that this state be only entered, when the PCIe device is deliberately put into test mode. However, we do not do this so it must be some kind of Keystone-proprietary behaviour. The effect is only observed on one out of many boards and only when the board is in a certain temperature range. So it's most likely either a production defect or bug in the physical design of the board.

My questions are:

  • Does anyone have a hint how/where to (physically/electrically) investigate further?
  • What could lead a Keystone II to enter POLL_COMPLIANCE state if test mode is NOT activated?

Cheers,
Gerald

  • Hi, Gerald,

    I am currently on a business trip and can't access my Linux machine to look at the code. After I am back to office, I'll check under what condition will it set the status to POLL_COMPLIANCE. Then, I'll talk to hardware expert to see if there is anything to do with hardware. I'll get back to you as soon as I have info.

    Rex

  • Hi, Gerald,

    Sorry for the slow response. I had a discussion with coworker. In the past, we had seen cases that the status gets stuck at POLL_COMPILANCE in non-test mode. Our experience is that it may be caused by signal integrity or clock jitter which is above tolerable range. You may want to check the clock source and measure its jitte to see if the status transition out if jitter improves.

    Rex