OMAP 3530 - GPMC burst reads with sDMA

OMAP3530 TRM Rev M page 989 said:

To support the burst mode, the logical channel must also be configured to use the source-port packed
access mode. The packed address mode cannot be used with a constant address mode: it must be
configured to use a post-increment address mode.

Looking at the 3730 TRM (rev I, section 11.4.5) it says

"Except in the constant addressing mode, the source or destination must be specified as
packed for burst transactions to occur."

This makes it sound like burst transactions are OK in constant adressing mode in the 3730, correct?

Another question regarding the constant address mode: to be able to burst 32 or 64 bytes, do I have to set up address pins/a memory region of the corresponding size or can it be smaller?  I.e., can I burst 64 bytes from a single-byte memory region?

Thanks,

Orjan

Orjan Friberg said:

Looking at the 3730 TRM (rev I, section 11.4.5) it says

"Except in the constant addressing mode, the source or destination must be specified as
packed for burst transactions to occur."

This makes it sound like burst transactions are OK in constant adressing mode in the 3730, correct?

That note is also present in the OMAP3530 documentation.  Just before it is this note:

"When a constant addressing mode is specified, only nonpacked accesses are used, and
specifying the accesses as packed has no effect."

I believe the note you mentioned says "except in the constant addressing mode" because in that mode accesses are always treated as non-packed.  FYI, I'm still a bit new to SDMA as my past experience has been primarilyt with EDMA...  I'm reading the same docs as you but my interpretation is that you cannot burst in the constant address mode.  Of course if you can see it happen on the silicon then I will change my mind!

Orjan Friberg said:

Another question regarding the constant address mode: to be able to burst 32 or 64 bytes, do I have to set up address pins/a memory region of the corresponding size or can it be smaller?  I.e., can I burst 64 bytes from a single-byte memory region?

Are you talking about having an 8-bit device on the GPMC?  If so, the GPMC will take care of converting a larger word in to 8-bit accesses.  However, you cannot burst 64 bytes due to the size of the FIFO built into the GPMC.  Please read the section called "L3 Interconnect Interface" inside the GPMC chapter.  In the OMAP3530 TRM spruf98p it is Section 11.1.4.2.

Brad

Brad,

Thanks for your reply.  We have things set up as multiplexed address/data,16-bit (so using post-increment mode for DMA burst is doable) in synchronous mode.  CPU reads seem to be working but for some reason the kernel thinks the GPMC_FCLK is 83 MHz (I'm pretty sure the L3 block is clocked at 166 MHz).  With the clock divider set to 0 we see on the 'scope that GPMC_CLK is 166 MHz.  That particular issue may be a topic for another thread though.

Thanks,

Orjan

Orjan, just a note that the max clock freq of GPMC_CLK is 100MHz.  You should not be setting your GPMC_CLK to 166MHz.

Regards,

James

James,

Thanks for the warning; we have set the clock divider correctly now and are running at 83 MHz.

We have DMA working now as well (64 kB transfers).  I'm getting around 24 MB/s but this is without DMA burst enabled, nor have we tried optimize the timing.  We should probably double check the timing values to avoid hogging the memory bus unnecessarily.

Thanks,

Orjan

Midson,

You're asking if a single DMA burst can be larger than 64 bytes, correct?  In reading the TRM, the maximum burst size is 16 and the maximum data size is 32 bits, so no if I'm understanding things correctly.

The 64 kB transfer I have set up I'm pretty sure is accomplished through multiple DMA bursts (I'm using 16 bit data, burst length 8).

Thanks Orjan. In one of the old entry, you mentioned that you got 24MB with-out DMA. Can you share throughput after using the DMA?

When I am using DMA, there is delay between the write burst and read burst. And it is increasing with no of frame per burst. Did you noticed that? 

24 MB/s was with DMA, but without DMA burst enabled.  Using burst size 4 we got ~64 MB/s, it was slightly faster with burst size 8 (same on src and dst).

Regarding the delay between bursts, I believe I saw another thread on the forum explaining that; it's not something I have looked at.

Thanks Orjan. I hope, MB == Mega Bytes and 60MB is bi-directional (30+30). Am I correct? 

The transfer rate in that example is for a unidirectional transfer (only reading).  But yes on MB == megabytes.

Thanks Orjan. Currently we are setting the DMA4_CSDP bit to enable the DMA Burst. Are you referring the same, for the DMA Burst mode  and Burst size 4 is basically 4x32? If our understanding is not correct, please give some more info on DMA Burst mode. Do I need to specifically set any other DMA registers?

could you send a complete code about this driver to me in private.I am new to this area and need a fast learning.I have seen a lot of materials about burst read,how about burst write?

hi,I want to know how the call back function works,if i call the omap_request_dma(OMAP24XX_DMA_GPMC, "FPGA rcv", your_fpga_dma_cb, info, &info->dma_channel_num);,,cause its definiton, your_fpga_dma_cb is the call back function,it has three params,what the values of these params?how these params are givin values.ps,is the info the data transfered?if it is,our data is a struct?what does this struct definition in common?when u set the data to be transfered by DMA,is it a DMA read or write?

 I am looking forward to your reply.please answer me ASAP.ps,is your code woring in kernel space or user space.

hi,I think u have achieved the results of communication using DMA burst and GPMC,could send me a code demo?or a code demo of the commmunication using DMA from RAM to RAM.My email address is arlene0606@gmail.com.Thanks a lot .I am looking forward to your reply.Please answer ASAP.

Hi Joe Joe,

Thanks for the informative post.  Looks like you've accomplished quite a lot with this interface.

I am having a similar problem that you had back when you wrote this.  Basically, I am using the AAD GPMC mode.  I am able to transmit a 32bit word as two 16bit transmissions.  These transmissions occur on the first two clock cycles after the address setup.

Like you, I am unable to transmit more than one 32 bit word.  In fact, my logic analyzer measurement is exactly like page 3230 of the TRM, revision O.  There is one major exception though.  I get D0 and D1.  D2-D7 are missing.

Any suggestions on how to write more than one word to the interface?

3125.Burst.pdf

These two links seem to have the info required...

http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/t/36314.aspx

http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/p/43106/323326.aspx#323326

In fact, now I have a prototype working burst: 7848.Working_Burst.pdf

Once I got it working, I was able to tighten up the timing a little bit.  Fun fact though, when using the DMA, the timing parameters are different.  What I mean is that with the very same timing settings, I get two different looking curves on my logic analyzer when driving the port from user space and from DMA land.  (I will update again should I find that this is no longer the case/or a solution is found).

Thank You,

terpaccount

ret = gpmc_cs_request(CS, SZ_16M, &cs_mem_base);
if (ret < 0)
{
printk(KERN_INFO "Failed to request GPMC mem for CS\n");
return -1;
}
printk(KERN_INFO "cs_mem_base:%lx\n", cs_mem_base);

ret = gpmc_cs_set_timings(CS, &timing);
if(ret != 0) {
printk(KERN_INFO "bad set timing %d\n", ret);
gpmc_cs_free(CS);
return -1;
}

gpmc_cs_base = ioremap(cs_mem_base, SZ_16M);
printk(KERN_INFO "gpmc_cs_base 0xff and 0x00 :%x\n", gpmc_cs_base);
while(true)
{
 read_data(data++,addr);
 addr=addr+2;
}

unsigned char read_data(unsigned char addr)
{
unsigned char val= *(gpmc_cs_base+addr);
return val;
}

struct gpmc_timings timing = {
 .sync_clk = 20, 

 .cs_on = 15,
 .cs_wr_off = 165, 
 .cs_rd_off = 130,

 .adv_on = 5,
 .adv_rd_off = 5,
 .adv_wr_off = 5,

 .we_on = 52, 
 .we_off = 127, 

 .oe_on = 5, 
 .oe_off = 135, 

 .page_burst_access = 5,
 .access = 8, 
 .rd_cycle = 180
 .wr_cycle = 180,

 .wr_access = 0,
 .wr_data_mux_bus = 0,
} 

I want to do async signal read,but the CS3 and RE line seen through the oscliscope are always high, it seems the read procedure dosen't work.but  with the same code the write thing is OK.could you give me a hint about what I did wrong?Thanks a lot.

First, please change your settings from decimal to hex.  That way you can see the settings more easily on in the TRM.

Second, adv_on should not equal adv_**_off.

Also, what about read cycle time?  Read access time?

.access = 8,
.rd_cycle = 180

don't you use the same way as mine to set the timing?.access is the read_access time,.rd_cycle is the read_cycle time

No, actually, I did not use the built in functions to set the register values.  Instead, I manually memory map the GPMC registers into the Kernel space, then set each register to the desired value.  Finally, I release the memory.

I did it this way because I felt that it was the clearest way know exactly what setting was used.

Also, please go through each of there rules and verify that you are not violating any of them: http://processors.wiki.ti.com/index.php/Tips_for_configuring_OMAP35x_and_AM-DM37x_GPMC_registers

Thanks a lot for your last help,these two days I met another strange thing.because I am not familiar with DMA,I have no idea about the hardware-sync,so I use the software-sync.below are the main code,but the CS and RD line has nothing to show.when i put  omap_start_dma(dma_channel_num);    in the cycle,write like while(true){ omap_start_dma(dma_channel_num);  },like this,I can see the CS and RD line turn up and down through the oscilliscpoe.I am looking forward your reply.

 /* DMA completion callback */
static void fpga_dma_cb(int channel_num, u16 ch_status, void *data)
{
}

dma_params.data_type = OMAP_DMA_DATA_TYPE_S16;
dma_params.src_amode = OMAP_DMA_AMODE_POST_INC;
dma_params.src_ei=1;
dma_params.src_fi=1;

dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC;
dma_params.dst_ei = 1;
dma_params.dst_fi = 1;
dma_params.read_prio=0;
dma_params.write_prio=0;

dma_params.elem_count = 240;
dma_params.frame_count = 160;
ret=omap_request_dma(0, "FPGA rcv", fpga_dma_cb, NULL, &dma_channel_num);
size = PAGE_ALIGN(size);
order=get_order(size);
struct page *page=alloc_pages(GFP_KERNEL | GFP_DMA, order);
unsigned char *ptr = page_address(page);
memset(ptr, 0, size);

omap_set_dma_dest_burst_mode(dma_channel_num,OMAP_DMA_DATA_BURST_16);
omap_set_dma_src_burst_mode(dma_channel_num,OMAP_DMA_DATA_BURST_16);
omap_set_dma_dest_data_pack(dma_channel_num,1);
omap_set_dma_src_data_pack(dma_channel_num,1);

dma_params.dst_start = __pa(ptr);
dma_params.src_start = cs_mem_base;
omap_set_dma_params(dma_channel_num, &dma_params);

omap_start_dma(dma_channel_num); 

sinceI do the single read and write well.but I met a problem when I do the sync burst read:

I export the function gpmc_cs_set_timings ,and add some code like below to do the sync burst read:

l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
    l=l|GPMC_CONFIG1_READTYPE_SYNC;
    l=l|GPMC_CONFIG1_READMULTIPLE_SUPP;
    l=l|GPMC_CONFIG1_CLKACTIVATIONTIME(1);
    gpmc_cs_write_reg(cs, GPMC_CS_CONFIG6, 0x0);

I call this function in my driver code,print the register,the result is look like below,I only want to do sync burst read,but I can't read anything on the D[0]-D[15] lines

I am looking forward to your reply.please help me,if you can give me some source code about sync burst read,It would be better for me to understand.Thanks again.

GPMC_CS_CONFIG1=62001001
GPMC_CS_CONFIG2=001c0b00
GPMC_CS_CONFIG3=00010900
GPMC_CS_CONFIG4=16090b00
GPMC_CS_CONFIG5=02091e0b
GPMC_CS_CONFIG6=00000000
GPMC_CS_CONFIG7=00000f6c