Warm reset ..continue

DavidVescovi

Other Parts Discussed in Thread: OMAP3530

I was trying to implement the workaround described to get a warm reset with memory retained. see http://e2e.ti.com/support/embedded/f/353/t/63069.aspx

I was trying to implement in the OALIoCtlHalReboot function which does set the GLOBAL SOFTWARE RESET at the end.

I can do step 1 to enable self-refresh on idle request (which seems to be set in the startup code anyway).

But if I am executing out of DRAM (ala Windows CE or Linux) then won't step 2 kill the program in its tracks and you can never do step 3 or 4?

Is this true?

I guess you could put the workaround function in on-chip SRAM and jump to it but this seems a little messy?

Any insight?

over 14 years ago

0 DavidVescovi over 14 years ago

Genius 5470 points

I also tried disabling interrupts and flipping idle request to after the cache flush as suggested in the other post.

It does not work and just stalls ...probably at the while loop.

BOOL OALIoCtlHalReboot(
    UINT32 code,
    VOID *pInpBuffer,
    UINT32 inpSize,
    VOID *pOutBuffer,
    UINT32 outSize,
    UINT32 *pOutSize
    )
{
    OMAP_PRCM_GLOBAL_PRM_REGS *pGlobalPrmRegs = OALPAtoUA(OMAP_PRCM_GLOBAL_PRM_REGS_PA);
    OMAP_CONTEXT_RESTORE_REGS *pContextRestoreRegs = OALPAtoUA(OMAP_CONTEXT_RESTORE_REGS_PA);
OMAP_PRCM_CORE_CM_REGS *pPrcmCoreCM = OALPAtoUA(OMAP_PRCM_CORE_CM_REGS_PA);
    BOOL    bPowerOn = FALSE;

OALMSG(OAL_IOCTL&&OAL_FUNC, (L"+OALIoCtlHalReboot\r\n"));

// Perform a global SW reset
OALMSG(TRUE, (L"*** RESET ***\r\n"));

    // Disable KITL
#if (_WINCEOSVER<600)
    OALKitlPowerOff();
#else
    KITLIoctl(IOCTL_KITL_POWER_CALL, &bPowerOn, sizeof(bPowerOn), NULL, 0, NULL);
#endif

    // Clear context registers
    OUTREG32(&pContextRestoreRegs->BOOT_CONFIG_ADDR, 0);
    OUTREG32(&pContextRestoreRegs->PUBLIC_RESTORE_ADDR, 0);
    OUTREG32(&pContextRestoreRegs->SECURE_SRAM_RESTORE_ADDR, 0);
    OUTREG32(&pContextRestoreRegs->SDRC_MODULE_SEMAPHORE, 0);
    OUTREG32(&pContextRestoreRegs->PRCM_BLOCK_OFFSET, 0);
    OUTREG32(&pContextRestoreRegs->SDRC_BLOCK_OFFSET, 0);
    OUTREG32(&pContextRestoreRegs->OEM_CPU_INFO_DATA_PA, 0);
    OUTREG32(&pContextRestoreRegs->OEM_CPU_INFO_DATA_VA, 0);

INTERRUPTS_ENABLE(FALSE);

// Flush the cache
OEMCacheRangeFlush( NULL, 0, CACHE_SYNC_ALL );

//dv: Advisory 3.1.1.176 Accesses to DDR Stall in SDRC After a Warm-reset
// put SDRC in Idle
    CLRREG32(&pPrcmCoreCM->CM_ICLKEN1_CORE, CM_CLKEN_SDRC);
    while ((INREG32(&pPrcmCoreCM->CM_IDLEST1_CORE) & CM_IDLEST_ST_SDRC) != CM_IDLEST_ST_SDRC)

// Do warm reset
    OUTREG32(&pGlobalPrmRegs->PRM_RSTCTRL, /*RSTCTRL_RST_DPLL3|*/ RSTCTRL_RST_GS);

    // Should never get to this point...
    OALMSG(OAL_IOCTL&&OAL_FUNC, (L"-OALIoCtlHalReboot\r\n"));
    return TRUE;
}

0 Adeneo Embedded support team over 14 years ago in reply to DavidVescovi

Mastermind 9310 points

As you pointed out, the code for this workaround needs to be executed out of SRAM or the execution will stall right after you disable the SDRC clock. Some of the OAL functions are already implemented to run from SRAM, such as "OALUpdateCoreFreq" for instance (assembly language : \WINCE600\PLATFORM\COMMON\src\soc\COMMON_TI_V1\OMAP3530\OAL\CPUIDLE\cpu.s). You can look for this function to see how to implement your own SRAM-running function.

Also note that you will need to modify the XLDR bootloader to re-enable the SDRC ICLK and reset SMS and SDRC controllers before performing the DDR initialization.

Let us know if you make any progress.

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Warm reset ..continue