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Compiler/DRA76P: RVC freeze when jumping to kernel

Part Number: DRA76P


Tool/software: TI C/C++ Compiler

Hi,

Using SDK vision 03.02. with RVC use case.

We configure use case to use IPU1 core and DSP1.

The RVC works fine at u-boot side but when jumping to kernel (Android) the camera freeze.

here the cfg for sdk :


# Both IVAHD_INCLUDE & IPUMM_INCLUDE should not be set to "yes"
# Only one should be enabled to avoid IVA-HD resource conflict
IPUMM_INCLUDE=no
IVAHD_INCLUDE=no
VPE_INCLUDE=yes
DSS_INCLUDE=yes
AVB_INCLUDE=no
CAL_INCLUDE=yes

#
# Enable below macro to enable DCAN integration into Vision SDK.
#
DCAN_INCLUDE=no

CPU_IDLE_ENABLED=yes

ROBUST_RVC_INCLUDE=yes

and for dts 

/*
 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "actia_dra76-evm.dts"

/*
 * Reserving memory used by Vision SDK configured at
 * \vision_sdk\apps\build\tda2xx\mem_segment_definition_linux.xs
 * Address 0x84000000 - 0x93C03000 is used; reserving 0x10000000 (256MB) for NDK_MEM and
 *			SR1_FRAME_BUFFER_MEM covering 0x84000000 - 0x94000000
 * Address 0xA0000000 - 0xA0530000 of size 0x530000 for SR0, REMOTE_LOG_MEM,
 *			LINK_STATS_MEM, SYSTEM_IPC_SHM_MEM, HDVPSS_DESC_MEM,
 *			TRACE_BUF, EXC_DATA, and PM_DATA
 */
&reserved_mem{
	rvc_pool1: rvc1@0x84000000 {
		reg = <0x0 0x84000000 0x0 0x10000000>;
		status = "okay";
	};

	rvc_pool2: rvc2@0xA0000000 {
		reg = <0x0 0xA0000000 0x0 0x530000>;
		status = "okay";
	};
};

/*
 * Memory reserved for IOMMU table carveout 0xbfc00000 for length 0x100000
 * Page Table Address for IPU1   0xbfc00000
 * Page Table Address for IPU2   0xbfc08000
 * Page Table Address for DSP1   0xbfc10000
 * Page Table Address for DSP2   0xbfc18000
 */
&reserved_mem {
	latea_pagetbl: late_pgtbl@bfc00000 {
		reg = <0x0 0xbfc00000 0x0 0x100000>;
		no-map;
		status = "okay";
	};
};


&mbox_ipu1_ipc3x {
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&mmu_ipu1 {
	ti,late-attach;
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};


&ipu1 {
	ti,late-attach;
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};


&dsp1 {
	ti,late-attach;
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&mmu0_dsp1 {
	ti,late-attach;
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&mmu1_dsp1 {
	ti,late-attach;
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&dsp1_cma_pool {
	reg = <0x0 0xa1000000 0x0 0x02000000>;
};

&mbox_dsp1_ipc3x {
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&mailbox5 {
        ti,no-reset-on-init;
        ti,no-idle-on-init;
};

&mailbox7 {
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&vip1 {
	status = "disabled";
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&vin1a {
	status = "disabled";
};

&vpe{
	status = "disabled";
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&isl79987 {
	status = "disabled";
};

&dispc{
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&dss {
	/delete-property/ ti,enable-opt-clks-on-reset;
	ti,no-reset-on-init;
	ti,no-idle-on-init;
	is_shared=<1>;
};


&timer7{
        ti,late-attach;
        ti,no-reset-on-init;
        ti,no-idle-on-init;
};

&timer5{
	ti,late-attach;
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&timer6{
	ti,late-attach;
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&timer8{
        ti,late-attach;
        ti,no-reset-on-init;
        ti,no-idle-on-init;
};


&timer10{
	ti,late-attach;
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&timer11{
	ti,late-attach;
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};


&ipu1_cma_pool {
	reg = <0x0 0x9e000000 0x0 0x02000000>;
};

&dsp2_cma_pool {
	reg = <0x0 0xa3000000 0x0 0x02000000>;
};

/* Set the default value of the GPIO to be
 * high instead of default low. Otherwise, the LCD
 * backlight briefly turns off and turns on
 * again.
 */
#if 0
&gpio4 {
	p1 {
		gpio-hog;
		gpios = <1 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "CON_LCD_PWR_DN";
	};
};

#endif

Regards,

Chokri