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CCS/TMS320C6678: The SRIO interface is not ok between FPGA and TMS320C6678

xiang song
Intellectual 770 points
Part Number: TMS320C6678
Other Parts Discussed in Thread: UCD9222, UCD7242

Tool/software: Code Composer Studio

hi all:

I have designed a custom board(board A), with two FPGAs: 7K325T and 7V690T, also with one DSP: TMS320C6678.

Now the power supplys and clocks for DSP is controlled by 7K325T, with the programmed bit, the DSP is initialized successfully.

All interfaces without SRIO(between 7V690T and C6678) word ok, include PCIE,SPI, I2C,EMIF (GE and Hyperlink is not used, so not connect). 

The SRIO interface between 7K325T and 7V690T is ok, so I think the circuit of 7V690T is OK.

I try to  initialise c6678 with 4 x1 1.25G interface, link can also not set up.

I have checked the electric circuit, nothing found.

I have another custom board(board B) with two 7V415T and two TMS320C6678, also with SRIO between FPGA and DSP. The srio interface test codes of DSP is ok on this board , so I thinks the codes is OK.

The differences between two custom  board is as follow:

1)board A is TMS320C6678ACYP, and board B is TMS320C6678ACYPA;

2) Board A uses UCD9222+UCD7242 to supply CVDD and CVDD1, other powers are powered by LTM4644.

   Board B use UCD9222+UCD7242 to supply CVDD of two DSPs, other powers are powered by LTM4644.

3) Board B use GE and Hyperlink interface, so corresponding pins are connected.

Can you give me some advise for this question?

Thanks.

Best wishes!

  • 0
    TI__Mastermind 42545 points

    Hi Xiang,

    It is difficult to debug these types of problems from a distance.  You are using a different FPGA and a different board so the issue may be with the SRIO implementation in the 7V690T or it could be a routing issue on the board. I don't think the power differences you mentioned would have any effect.  Are you using the same clocking scheme and generator? Is there a significant difference in the routing between the two boards, ie length, layers, reference planes?  Does the SRIO operate if you attempt to run the interface at a slower speed?

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 770 points

    hi Bill:

    Thanks for your reply.

    Now I try to make the reference clock of FPGA and the reference clock of DSP from the same  crystal, then the link is OK, the lan speed can run at x5 5.0Gbps. But it is not needed for the SRIO link partner with the same reference clock source.

    Thanks.

    Best wishes!

    xiang song.

  • 0 in reply to xiang song
    TI__Mastermind 42545 points

    Hi Xiang Song,

    Generally, if the interface is working with a common clock but not working with separate clocks than one or both sides of the interface has a clock source that doesn't meet the jitter requirements.  I am happy you were able to get the link working with a common clock.  Is that a workable solution for you?

    Regards, Bill