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66AK2H12: Concurrent DDR access

SamSeytani
Intellectual 535 points
Part Number: 66AK2H12

Hello all,

As i read the document in the link https://processors.wiki.ti.com/index.php/Keystone_SoC_Level_Optimizations , a question came to my mind.

Regarding to this figure https://processors.wiki.ti.com/index.php/File:6678_TeraNet_Composite_Markup.png , there seems to be a concurrent access to DDR from MSMC (see yellow and blue lines).

1-) Is that concurrent transfer possible? Can you explain it further?

2-) Also if i want to read seperate data from DDR to each of the DSP cores. Can all the DDR commands arrive to DDR simultaneosly or is it arbitrated at the MSMC before sending to DDR?

I'm looking forward to your answers.

Thank you,

Best.

  • 0
    Intellectual 535 points

    In addition to that questions, i have some questions regarding arbitration mechanism.

    For example some core simultaneously wants to write to DDR3 memory but in different addresses.

    As i understand, the commands are first arbitrated with MDMA arbitration register for each core.

    Then the commands arrive to MSMC. Here the commands are arbitrated according to the same priority value that MDMA arbitration register has but also with a starvation bound register. Commands are than forwarded to DDR EMIF from the MSMC Master EMIF port. 

    When the commands arrive at DDR, COS and PR_OLD_COUNT values comes in attention but the assigned priorities remains same (assigned with MDMAARBD).

    3-) Is that correct?

    4-) And what is the bus width between MSMC EMIF port and DDR EMIF? In a document i saw 64 bits, ,n another one 128 bits.

    Thank you,

    Best.

  • 0
    TI__Guru* 95265 points

    Hi,

    There can be a concurrent access, just from another master. For example, one access over the XMC x n comes from a CPU core. Another access comes from EDMA ------>Teranet_3_a----->bridge 5.

    For the arbitration, please see the Keystone II DDR3 controller user guide, SPRUHN7C, 2.6.1 Arbitration

    Regards, Eric

  • 0 in reply to lding
    Intellectual 535 points

    I clicked "This resolved my issue" by mistake. I am still looking for answers for the other questions.

    Thanks.

  • 0 in reply to SamSeytani
    TI__Guru* 95265 points

    Hi,

    3) The arbitration is correct.

    4) The bandwidth between MSMC EMIF and DDR EMIF interface is 256-bit. This is from what I saw in Figure 2-1 MSMC Functional Block Diagram of 

    KeyStone II Architecture
    Literature Number: SPRUHJ6
    November 2012
    Multicore Shared Memory Controller (MSMC)
    User Guide

    Which docs showed 64-bit or 128-bit?

    Regards, Eric

  • 0 in reply to lding
    Intellectual 535 points

    8475.8371.K2 SOC Memory Performance.doc

    In this document is seems to be 64 bits. 128bit is by mistake please ignore it.

    Is there an updated version of this document?

  • 0 in reply to SamSeytani
    TI__Guru* 95265 points

    Hi,

    Thanks for pointing out this document! It was developed by a few TI engineers but it was not officially published, so it will not be corrected. DDR3 chip is 64-bit , maybe this is the reason that the document wrote 64-bit in between MSMC and EMIF. This 64-bit is used for DDR3 bandwidth calculation.

    Instead, a formal one for KS II performance is online here:  http://www.ti.com/lit/an/sprabk5b/sprabk5b.pdf.

    Regards, Eric

  • 0 in reply to lding
    Intellectual 535 points
    Where are the DDR3A and DDR3B located? I think when I access 0x80000000 from DSP, by default I access DDR3A right?
  • 0 in reply to SamSeytani
    TI__Guru* 95265 points

    Hi,

    Please see the K2H datasheet for memory map.

    Seeing from 0x8000_0000 on DSP core is DDR3B. But, if you have the MPAX setting to convert Physical address from 0x8:0000:0000 into logical 0x8000:0000, then what you saw is DDR3A address. If you use the GEL file on DSP for initialization, this has the MPAX set-up. Or, you can double check DSP core address 0x0800:0000 region for the MPAX set-up to confirm.

    Regards, Eric