Other Parts Discussed in Thread: PMP
Hi,
I am using AM5718 IDK EVM and ti-processor-sdk-linux-am57xx-evm-05.03.00.07.
We have developed a custom board based on AM5718.
In the board, we have run diagnostics for memory test and sd-card. We have also established connection via JTAG. We have verified UART3, QSPI, GPIOs etc. We have programmed board details to EEPROM also.
We have enabled pin-mux of minimum peripherals in our board( ddr, DEBUGSS , GMAC_MDIO, GMAC_SW0, 1 GPIO, MMC1, I2C, OSC0, PRCM,QSPI and UART3). The pin-mux file is given in mux_data.h.
We have disabled most of the nodes (like gpmc, mcasp, rtc, pciephy, qspi, spi, pruss, mailbox...) from DTB and our combined dts is attached in am571x-idk.dts (converted am571x-idk. dtb to dts).
In the custom board we have maintained the following designs as in EVM
� U-Boot SPL 2018.01 (Feb 03 2020 - 11:22:17) DRA722-GP ES2.0 Trying to boot from MMC1 no pinctrl state for default mode no pinctrl state for default mode Card did not respond to voltage select! *** Warning - MMC init failed, using default environment U-Boot 2018.01 (Feb 03 2020 - 11:22:17 +0530) CPU : DRA722-GP ES2.0 Model: TI AM5718 IDK Board: AM571x IDK REV 1.3B DRAM: 1 GiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 Card did not respond to voltage select! *** Warning - MMC init failed, using default environment Card did not respond to voltage select! invalid mmc device SCSI: SATA link 0 timeout. AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst scanning bus for devices... Found 0 device(s). Net: Could not get PHY for ethernet@48484000: addr 0 Warning: ethernet@48484000 using MAC address from ROM eth0: ethernet@48484000 Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device SD/MMC found on device 0 ** Unable to read file boot.scr ** 1490 bytes read in 2 ms (727.5 KiB/s) Loaded env from uEnv.txt Importing environment from mmc0 ... Running uenvcmd ... 1 bytes read in 2 ms (0 Bytes/s) Already setup. switch to partitions #0, OK mmc0 is current device SD/MMC found on device 0 4026880 bytes read in 290 ms (13.2 MiB/s) 97137 bytes read in 56 ms (1.7 MiB/s) ## Flattened Device Tree blob at 88000000 Booting using the fdt blob at 0x88000000 Loading Device Tree to 8ffe5000, end 8ffffb70 ... OK Starting kernel ...
U-Boot 2018.01 (Feb 03 2020 - 11:22:17 +0530)
CPU : DRA722-GP ES2.0
Model: TI AM5718 IDK
Board: AM571x IDK REV 1.3B
DRAM: 1 GiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
Card did not respond to voltage select!
*** Warning - MMC init failed, using default environment
Card did not respond to voltage select!
invalid mmc device
SCSI: SATA link 0 timeout.
AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst
scanning bus for devices...
Found 0 device(s).
Net: Could not get PHY for ethernet@48484000: addr 0
Warning: ethernet@48484000 using MAC address from ROM
eth0: ethernet@48484000
Hit any key to stop autoboot: 0
=> printenv
arch=arm
args_mmc=run finduuid;setenv bootargs console=${console} ${optargs} root=PARTUUID=${uuid} rw rootfstype=${mmcrootfstype}
baudrate=115200
board=am57xx
board_name=am571x_idk
board_rev=1.3B
board_serial=21184P520344
boot_fdt=try
boot_fit=0
bootargs=androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=am57xevmboard
bootcmd=if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo B
bootdelay=2
bootdir=/boot
bootenvfile=uEnv.txt
bootfile=zImage
bootm_size=0x10000000
bootpart=0:2
bootscript=echo Running bootscript from mmc${mmcdev} ...; source ${loadaddr}
console=ttyO2,115200n8
cpu=armv7
dfu_alt_info_emmc=rawemmc raw 0 3751936;boot part 1 1;rootfs part 1 2;MLO fat 1 1;MLO.raw raw 0x100 0x200;u-boot.img.raw raw 0x300 01
dfu_alt_info_mmc=boot part 0 1;rootfs part 0 2;MLO fat 0 1;MLO.raw raw 0x100 0x200;u-boot.img.raw raw 0x300 0x1000;u-env.raw raw 0x11
dfu_alt_info_ram=kernel ram 0x80200000 0x4000000;fdt ram 0x80f80000 0x80000;ramdisk ram 0x81000000 0x4000000
dfu_bufsiz=0x10000
dofastboot=0
emmc_android_boot=echo Trying to boot Android from eMMC ...; run update_to_fit; setenv eval_bootargs setenv bootargs $bootargs; run ;
emmc_linux_boot=echo Trying to boot Linux from eMMC ...; setenv mmcdev 1; setenv bootpart 1:2; setenv mmcroot /dev/mmcblk0p2 rw; run;
envboot=mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device ${mmcdev};if run loadbootscript; then run bootscript;else;
ethaddr=40:06:a0:bb:b6:52
fastboot.board_rev=1.3B
fastboot.cpu=DRA722
fastboot.secure=GP
fdt_addr_r=0x88000000
fdtaddr=0x88000000
fdtcontroladdr=bdf17578
fdtfile=undefined
findfdt=if test $board_name = omap5_uevm; then setenv fdtfile omap5-uevm.dtb; fi; if test $board_name = dra7xx; then setenv fdtfile
finduuid=part uuid mmc ${bootpart} uuid
fit_bootfile=fitImage
fit_loadaddr=0x87000000
idk_lcd=no
importbootenv=echo Importing environment from mmc${mmcdev} ...; env import -t ${loadaddr} ${filesize}
kernel_addr_r=0x82000000
loadaddr=0x82000000
loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}
loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr
loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}
loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};
loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}
mmcboot=mmc dev ${mmcdev}; setenv devnum ${mmcdev}; setenv devtype mmc; if mmc rescan; then echo SD/MMC found on device ${mmcdev};if;
mmcdev=0
mmcloados=run args_mmc; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if run loadfdt; then bootz ${loadaddr} - ${fdtaddr;
mmcrootfstype=ext4 rootwait
netargs=setenv bootargs console=${console} ${optargs} root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp
netboot=echo Booting from network ...; setenv autoload no; dhcp; run netloadimage; run netloadfdt; run netargs; bootz ${loadaddr} - }
netloadfdt=tftp ${fdtaddr} ${fdtfile}
netloadimage=tftp ${loadaddr} ${bootfile}
nfsopts=nolock
partitions=uuid_disk=${uuid_gpt_disk};name=bootloader,start=384K,size=1792K,uuid=${uuid_gpt_bootloader};name=rootfs,start=2688K,size}
partitions_android=uuid_disk=${uuid_gpt_disk};name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};name=bootloader,size=1792K,}
pxefile_addr_r=0x80100000
ramdisk_addr_r=0x88080000
rdaddr=0x88080000
rootpath=/export/rootfs
scriptaddr=0x80000000
scsidevs=0
serial#=18015010540842e1
soc=omap5
static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off
stderr=serial@48020000
stdin=serial@48020000
stdout=serial@48020000
update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}
usbtty=cdc_acm
vendor=ti
ver=U-Boot 2018.01 (Feb 03 2020 - 11:22:17 +0530)
vram=16M
Environment size: 7764/131067 bytes
=> ddr test 0x80000000 0xbdf15000
Please wait ...
ddr memory test PASSED!
=>
1. MMC1 (SD card),
2. PMIC (TPS6590379) with PMIC_INT mapped to different GPIO,
3. EEPROM ,
4. QSPI
5. UART
6. GMAC Ethernet with Reset control via (GPIO) (deviation from EVM design)
/*
*
* HW data initialization for OMAP5
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* Sricharan R <r.sricharan@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <palmas.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/arch/clock.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
#include <asm/emif.h>
struct prcm_regs const **prcm =
(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
struct dplls const **dplls_data =
(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
struct vcores_data const **omap_vcores =
(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
struct omap_sys_ctrl_regs const **ctrl =
(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
/* OPP NOM FREQUENCY for ES1.0 */
static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
{250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
{266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
{277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
{368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
{266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
{277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
{368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
};
static const struct dpll_params
core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
{266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
{266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
{443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
{277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
{368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
{32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
{32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
{32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
{96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
{160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = {
{32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 12 MHz */
{96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 20 MHz */
{160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
{1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
{49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
#endif
/* ABE M & N values with 32K clock as source */
#ifndef CONFIG_SYS_OMAP_ABE_SYSCK
static const struct dpll_params abe_dpll_params_32k_196608khz = {
750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
};
#endif
/* ABE M & N values with sysclk2(22.5792 MHz) as input */
static const struct dpll_params
abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
{111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
{266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
{250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
{250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
{119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
struct dplls omap5_dplls_es1 = {
.mpu = mpu_dpll_params_800mhz,
.core = core_dpll_params_2128mhz_ddr532,
.per = per_dpll_params_768mhz,
.iva = iva_dpll_params_2330mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls omap5_dplls_es2 = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_ddr532_es2,
.per = per_dpll_params_768mhz_es2,
.iva = iva_dpll_params_2330mhz,
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
.abe = abe_dpll_params_sysclk_196608khz,
#else
.abe = &abe_dpll_params_32k_196608khz,
#endif
.usb = usb_dpll_params_1920mhz,
.ddr = NULL
};
struct dplls dra76x_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
.per = per_dpll_params_768mhz_dra76x,
.abe = abe_dpll_params_sysclk2_361267khz,
.iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_2664mhz,
.gmac = gmac_dpll_params_2000mhz,
};
struct dplls dra7xx_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
.per = per_dpll_params_768mhz_dra7xx,
.abe = abe_dpll_params_sysclk2_361267khz,
.iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_2128mhz,
.gmac = gmac_dpll_params_2000mhz,
};
struct dplls dra72x_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
.per = per_dpll_params_768mhz_dra7xx,
.abe = abe_dpll_params_sysclk2_361267khz,
.iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_2664mhz,
.gmac = gmac_dpll_params_2000mhz,
};
struct pmic_data palmas = {
.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
.step = 10000, /* 10 mV represented in uV */
/*
* Offset codes 1-6 all give the base voltage in Palmas
* Offset code 0 switches OFF the SMPS
*/
.start_code = 6,
.i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
.pmic_bus_init = sri2c_init,
.pmic_write = omap_vc_bypass_send_value,
.gpio_en = 0,
};
/* The TPS659038 and TPS65917 are software-compatible, use common struct */
struct pmic_data tps659038 = {
.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
.step = 10000, /* 10 mV represented in uV */
/*
* Offset codes 1-6 all give the base voltage in Palmas
* Offset code 0 switches OFF the SMPS
*/
.start_code = 6,
.i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
.pmic_bus_init = gpi2c_init,
.pmic_write = palmas_i2c_write_u8,
.gpio_en = 0,
};
/* The LP87565*/
struct pmic_data lp87565 = {
.base_offset = LP873X_BUCK_BASE_VOLT_UV,
.step = 5000, /* 5 mV represented in uV */
/*
* Offset codes 0 - 0x13 Invalid.
* Offset codes 0x14 0x17 give 10mV steps
* Offset codes 0x17 through 0x9D give 5mV steps
* So let us start with our operating range from .73V
*/
.start_code = 0x17,
.i2c_slave_addr = 0x60,
.pmic_bus_init = gpi2c_init,
.pmic_write = palmas_i2c_write_u8,
};
/* The LP8732 and LP8733 are software-compatible, use common struct */
struct pmic_data lp8733 = {
.base_offset = LP873X_BUCK_BASE_VOLT_UV,
.step = 5000, /* 5 mV represented in uV */
/*
* Offset codes 0 - 0x13 Invalid.
* Offset codes 0x14 0x17 give 10mV steps
* Offset codes 0x17 through 0x9D give 5mV steps
* So let us start with our operating range from .73V
*/
.start_code = 0x17,
.i2c_slave_addr = 0x60,
.pmic_bus_init = gpi2c_init,
.pmic_write = palmas_i2c_write_u8,
};
struct vcores_data omap5430_volts = {
.mpu.value[OPP_NOM] = VDD_MPU,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
.mpu.pmic = &palmas,
.core.value[OPP_NOM] = VDD_CORE,
.core.addr = SMPS_REG_ADDR_8_CORE,
.core.pmic = &palmas,
.mm.value[OPP_NOM] = VDD_MM,
.mm.addr = SMPS_REG_ADDR_45_IVA,
.mm.pmic = &palmas,
};
struct vcores_data omap5430_volts_es2 = {
.mpu.value[OPP_NOM] = VDD_MPU_ES2,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
.mpu.pmic = &palmas,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.core.value[OPP_NOM] = VDD_CORE_ES2,
.core.addr = SMPS_REG_ADDR_8_CORE,
.core.pmic = &palmas,
.mm.value[OPP_NOM] = VDD_MM_ES2,
.mm.addr = SMPS_REG_ADDR_45_IVA,
.mm.pmic = &palmas,
.mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
.mpu.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MPU_OPNO_VMIN,
.mpu.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS,
.core.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_CORE_OPNO_VMIN,
.core.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS,
.mm.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MM_OPNO_VMIN,
.mm.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS,
};
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*/
void enable_basic_clocks(void)
{
u32 const clk_domains_essential[] = {
(*prcm)->cm_l4per_clkstctrl,
(*prcm)->cm_l3init_clkstctrl,
(*prcm)->cm_memif_clkstctrl,
(*prcm)->cm_l4cfg_clkstctrl,
#ifdef CONFIG_DRIVER_TI_CPSW
(*prcm)->cm_gmac_clkstctrl,
#endif
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3_gpmc_clkctrl,
(*prcm)->cm_memif_emif_1_clkctrl,
(*prcm)->cm_memif_emif_2_clkctrl,
(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
(*prcm)->cm_wkup_gpio1_clkctrl,
(*prcm)->cm_l4per_gpio2_clkctrl,
(*prcm)->cm_l4per_gpio3_clkctrl,
(*prcm)->cm_l4per_gpio4_clkctrl,
(*prcm)->cm_l4per_gpio5_clkctrl,
(*prcm)->cm_l4per_gpio6_clkctrl,
(*prcm)->cm_l4per_gpio7_clkctrl,
(*prcm)->cm_l4per_gpio8_clkctrl,
#ifdef CONFIG_SCSI_AHCI_PLAT
(*prcm)->cm_l3init_ocp2scp3_clkctrl,
#endif
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_wkup_gptimer1_clkctrl,
(*prcm)->cm_l3init_hsmmc1_clkctrl,
(*prcm)->cm_l3init_hsmmc2_clkctrl,
(*prcm)->cm_l4per_gptimer2_clkctrl,
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_l4per_uart3_clkctrl,
(*prcm)->cm_l4per_i2c1_clkctrl,
#ifdef CONFIG_DRIVER_TI_CPSW
(*prcm)->cm_gmac_gmac_clkctrl,
#endif
#ifdef CONFIG_TI_QSPI
(*prcm)->cm_l4per_qspi_clkctrl,
#endif
#ifdef CONFIG_SCSI_AHCI_PLAT
(*prcm)->cm_l3init_sata_clkctrl,
#endif
0
};
/* Enable optional additional functional clock for GPIO4 */
setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
/* Enable 192 MHz clock for MMC1 & MMC2 */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
/* Set the correct clock dividers for mmc */
clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
/* Select 32KHz clock as the source of GPTIMER1 */
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
GPTIMER1_CLKCTRL_CLKSEL_MASK);
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
#ifdef CONFIG_TI_QSPI
setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
#endif
#ifdef CONFIG_SCSI_AHCI_PLAT
/* Enable optional functional clock for SATA */
setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
SATA_CLKCTRL_OPTFCLKEN_MASK);
#endif
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_CORE_MASK);
}
void enable_basic_uboot_clocks(void)
{
u32 const clk_domains_essential[] = {
#if defined(CONFIG_DRA7XX)
(*prcm)->cm_ipu_clkstctrl,
#endif
0
};
u32 const clk_modules_hw_auto_essential[] = {
(*prcm)->cm_l3init_hsusbtll_clkctrl,
0
};
u32 const clk_modules_explicit_en_essential[] = {
(*prcm)->cm_l4per_mcspi1_clkctrl,
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
#if defined(CONFIG_DRA7XX)
(*prcm)->cm_ipu_i2c5_clkctrl,
#else
(*prcm)->cm_l4per_i2c5_clkctrl,
#endif
(*prcm)->cm_l3init_hsusbhost_clkctrl,
(*prcm)->cm_l3init_fsusb_clkctrl,
0
};
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
1);
}
#ifdef CONFIG_TI_EDMA3
void enable_edma3_clocks(void)
{
u32 const clk_domains_edma3[] = {
0
};
u32 const clk_modules_hw_auto_edma3[] = {
(*prcm)->cm_l3main1_tptc1_clkctrl,
(*prcm)->cm_l3main1_tptc2_clkctrl,
0
};
u32 const clk_modules_explicit_en_edma3[] = {
0
};
do_enable_clocks(clk_domains_edma3,
clk_modules_hw_auto_edma3,
clk_modules_explicit_en_edma3,
1);
}
void disable_edma3_clocks(void)
{
u32 const clk_domains_edma3[] = {
0
};
u32 const clk_modules_disable_edma3[] = {
(*prcm)->cm_l3main1_tptc1_clkctrl,
(*prcm)->cm_l3main1_tptc2_clkctrl,
0
};
do_disable_clocks(clk_domains_edma3,
clk_modules_disable_edma3,
1);
}
#endif
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
void enable_usb_clocks(int index)
{
u32 cm_l3init_usb_otg_ss_clkctrl = 0;
if (index == 0) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
/* Enable 960 MHz clock for dwc3 */
setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
OPTFCLKEN_REFCLK960M);
/* Enable 32 KHz clock for USB_PHY1 */
setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
/* Enable 32 KHz clock for USB_PHY3 */
if (is_dra7xx())
setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
} else if (index == 1) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
/* Enable 960 MHz clock for dwc3 */
setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
OPTFCLKEN_REFCLK960M);
/* Enable 32 KHz clock for dwc3 */
setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
/* Enable 60 MHz clock for USB2PHY2 */
setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
}
u32 const clk_domains_usb[] = {
0
};
u32 const clk_modules_hw_auto_usb[] = {
(*prcm)->cm_l3init_ocp2scp1_clkctrl,
cm_l3init_usb_otg_ss_clkctrl,
0
};
u32 const clk_modules_explicit_en_usb[] = {
0
};
do_enable_clocks(clk_domains_usb,
clk_modules_hw_auto_usb,
clk_modules_explicit_en_usb,
1);
}
void disable_usb_clocks(int index)
{
u32 cm_l3init_usb_otg_ss_clkctrl = 0;
if (index == 0) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
/* Disable 960 MHz clock for dwc3 */
clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
OPTFCLKEN_REFCLK960M);
/* Disable 32 KHz clock for USB_PHY1 */
clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
/* Disable 32 KHz clock for USB_PHY3 */
if (is_dra7xx())
clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
} else if (index == 1) {
cm_l3init_usb_otg_ss_clkctrl =
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
/* Disable 960 MHz clock for dwc3 */
clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
OPTFCLKEN_REFCLK960M);
/* Disable 32 KHz clock for dwc3 */
clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
/* Disable 60 MHz clock for USB2PHY2 */
clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
}
u32 const clk_domains_usb[] = {
0
};
u32 const clk_modules_disable[] = {
(*prcm)->cm_l3init_ocp2scp1_clkctrl,
cm_l3init_usb_otg_ss_clkctrl,
0
};
do_disable_clocks(clk_domains_usb,
clk_modules_disable,
1);
}
#endif
const struct ctrl_ioregs ioregs_omap5430 = {
.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
.ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
.ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
.ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
};
const struct ctrl_ioregs ioregs_omap5432_es1 = {
.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
.ctrl_lpddr2ch = 0x0,
.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
};
const struct ctrl_ioregs ioregs_omap5432_es2 = {
.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
.ctrl_lpddr2ch = 0x0,
.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
};
const struct ctrl_ioregs ioregs_dra7xx_es1 = {
.ctrl_ddrch = 0x40404040,
.ctrl_lpddr2ch = 0x40404040,
.ctrl_ddr3ch = 0x80808080,
.ctrl_ddrio_0 = 0x00094A40,
.ctrl_ddrio_1 = 0x04A52000,
.ctrl_ddrio_2 = 0x84210000,
.ctrl_emif_sdram_config_ext = 0x0001C1A7,
.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
const struct ctrl_ioregs ioregs_dra72x_es1 = {
.ctrl_ddrch = 0x40404040,
.ctrl_lpddr2ch = 0x40404040,
.ctrl_ddr3ch = 0x60606080,
.ctrl_ddrio_0 = 0x00094A40,
.ctrl_ddrio_1 = 0x04A52000,
.ctrl_ddrio_2 = 0x84210000,
.ctrl_emif_sdram_config_ext = 0x0001C1A7,
.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
const struct ctrl_ioregs ioregs_dra72x_es2 = {
.ctrl_ddrch = 0x40404040,
.ctrl_lpddr2ch = 0x40404040,
.ctrl_ddr3ch = 0x80808080,
.ctrl_ddrio_0 = 0x00094A40,
.ctrl_ddrio_1 = 0x00000000,
.ctrl_ddrio_2 = 0x00000000,
.ctrl_emif_sdram_config_ext = 0x0001C1A7,
.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
void __weak hw_data_init(void)
{
u32 omap_rev = omap_revision();
switch (omap_rev) {
case OMAP5430_ES1_0:
case OMAP5432_ES1_0:
*prcm = &omap5_es1_prcm;
*dplls_data = &omap5_dplls_es1;
*omap_vcores = &omap5430_volts;
*ctrl = &omap5_ctrl;
break;
case OMAP5430_ES2_0:
case OMAP5432_ES2_0:
*prcm = &omap5_es2_prcm;
*dplls_data = &omap5_dplls_es2;
*omap_vcores = &omap5430_volts_es2;
*ctrl = &omap5_ctrl;
break;
case DRA762_ABZ_ES1_0:
case DRA762_ACD_ES1_0:
case DRA762_ES1_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra76x_dplls;
*ctrl = &dra7xx_ctrl;
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra7xx_dplls;
*ctrl = &dra7xx_ctrl;
break;
case DRA722_ES1_0:
case DRA722_ES2_0:
case DRA722_ES2_1:
*prcm = &dra7xx_prcm;
*dplls_data = &dra72x_dplls;
*ctrl = &dra7xx_ctrl;
break;
default:
printf("\n INVALID OMAP REVISION ");
}
}
void __weak get_ioregs(const struct ctrl_ioregs **regs)
{
u32 omap_rev = omap_revision();
switch (omap_rev) {
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
*regs = &ioregs_omap5430;
break;
case OMAP5432_ES1_0:
*regs = &ioregs_omap5432_es1;
break;
case OMAP5432_ES2_0:
*regs = &ioregs_omap5432_es2;
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
case DRA762_ES1_0:
case DRA762_ACD_ES1_0:
case DRA762_ABZ_ES1_0:
*regs = &ioregs_dra7xx_es1;
break;
case DRA722_ES1_0:
*regs = &ioregs_dra72x_es1;
break;
case DRA722_ES2_0:
case DRA722_ES2_1:
*regs = &ioregs_dra72x_es2;
break;
default:
printf("\n INVALID OMAP REVISION ");
}
}
/*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
*
* Author: Felipe Balbi <balbi@ti.com>
*
* Based on board/ti/dra7xx/evm.c
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <palmas.h>
#include <sata.h>
#include <usb.h>
#include <asm/omap_common.h>
#include <asm/omap_sec_common.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch/dra7xx_iodelay.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
#include <asm/arch/gpio.h>
#include <asm/arch/omap.h>
#include <environment.h>
#include <usb.h>
#include <linux/usb/gadget.h>
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <ti-usb-phy-uboot.h>
#include <mmc.h>
#include "../common/board_detect.h"
#include "mux_data.h"
#define board_is_x15() board_ti_is("BBRDX15_")
#define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
!strncmp("B.10", board_ti_get_rev(), 3))
#define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
!strncmp("C.00", board_ti_get_rev(), 3))
#define board_is_am572x_evm() board_ti_is("AM572PM_")
#define board_is_am572x_evm_reva3() \
(board_ti_is("AM572PM_") && \
!strncmp("A.30", board_ti_get_rev(), 3))
#define board_is_am574x_idk() board_ti_is("AM574IDK")
#define board_is_am572x_idk() board_ti_is("AM572IDK")
#define board_is_am571x_idk() board_ti_is("AM571IDK")
#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
/* GPIO 7_11 */
#define GPIO_DDR_VTT_EN 203
/* Touch screen controller to identify the LCD */
#define OSD_TS_FT_BUS_ADDRESS 0
#define OSD_TS_FT_CHIP_ADDRESS 0x38
#define OSD_TS_FT_REG_ID 0xA3
/*
* Touchscreen IDs for various OSD panels
* Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
*/
/* Used on newer osd101t2587 Panels */
#define OSD_TS_FT_ID_5x46 0x54
/* Used on older osd101t2045 Panels */
#define OSD_TS_FT_ID_5606 0x08
#define SYSINFO_BOARD_NAME_MAX_LEN 45
#define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
#define TPS65903X_PAD2_POWERHOLD_MASK 0x20
const struct omap_sysinfo sysinfo = {
"Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
};
/* Changes for DDR starts here - Anupama */
const struct ctrl_ioregs AM571x_DDR3L_666MHz_TI_AM571x_IDK_ctrl_ioregs = {
.ctrl_ddr3ch = 0x60606060,
.ctrl_ddrch = 0x40404040,
.ctrl_ddrio_0 = 0x00094A40,
.ctrl_ddrio_1 = 0x00000000,
.ctrl_lpddr2ch = 0x00404000 ,
.ctrl_emif_sdram_config_ext = 0x0000C123
};
void get_ioregs(const struct ctrl_ioregs **regs)
{
*regs = &AM571x_DDR3L_666MHz_TI_AM571x_IDK_ctrl_ioregs;
}
const struct dmm_lisa_map_regs AM571x_DDR3L_666MHz_TI_AM571x_IDK_dmm_regs = {
.dmm_lisa_map_0 = 0x00000000,
.dmm_lisa_map_1 = 0x00000000,
.dmm_lisa_map_2 = 0x80600100,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
const struct emif_regs AM571x_DDR3L_666MHz_TI_AM571x_IDK_emif_regs = {
.sdram_config_init = 0x61862B32,
.sdram_config = 0x61862B32,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x0000514D,
.ref_ctrl_final = 0x0000144A,
.sdram_tim1 = 0xD33367EC,
.sdram_tim2 = 0x30B37FE3,
.sdram_tim3 = 0x409F8AD8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0824400E,
.emif_ddr_phy_ctlr_1 = 0x0E24400E,
.emif_rd_wr_exec_thresh = 0x00000305,
.emif_ecc_ctrl_reg = 0x00000000,
.emif_ecc_address_range_1 = 0x3FFF0000,
.emif_ecc_address_range_2 = 0x00000000,
};
const unsigned int AM571x_DDR3L_666MHz_TI_AM571x_IDK_emif1_ext_phy_regs [] = {
0x04040100, /* EMIF1_EXT_PHY_CTRL_1 */
0x006B00AA, /* EMIF1_EXT_PHY_CTRL_2 */
0x006B00A9, /* EMIF1_EXT_PHY_CTRL_3 */
0x006B00B8, /* EMIF1_EXT_PHY_CTRL_4 */
0x006B00B0, /* EMIF1_EXT_PHY_CTRL_5 */
0x006B00C1, /* EMIF1_EXT_PHY_CTRL_6 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_7 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_8 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_9 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_10 */
0x002F002F, /* EMIF1_EXT_PHY_CTRL_11 */
0x00600078, /* EMIF1_EXT_PHY_CTRL_12 */
0x00600078, /* EMIF1_EXT_PHY_CTRL_13 */
0x00600079, /* EMIF1_EXT_PHY_CTRL_14 */
0x00600080, /* EMIF1_EXT_PHY_CTRL_15 */
0x0060007D, /* EMIF1_EXT_PHY_CTRL_16 */
0x00400058, /* EMIF1_EXT_PHY_CTRL_17 */
0x00400058, /* EMIF1_EXT_PHY_CTRL_18 */
0x00400059, /* EMIF1_EXT_PHY_CTRL_19 */
0x00400060, /* EMIF1_EXT_PHY_CTRL_20 */
0x0040005D, /* EMIF1_EXT_PHY_CTRL_21 */
0x00800080, /* EMIF1_EXT_PHY_CTRL_22 */
0x00800080, /* EMIF1_EXT_PHY_CTRL_23 */
0x40010080, /* EMIF1_EXT_PHY_CTRL_24 */
0x08102040, /* EMIF1_EXT_PHY_CTRL_25 */
0x0000009A, /* EMIF1_EXT_PHY_CTRL_26 */
0x00000099, /* EMIF1_EXT_PHY_CTRL_27 */
0x000000A8, /* EMIF1_EXT_PHY_CTRL_28 */
0x000000A0, /* EMIF1_EXT_PHY_CTRL_29 */
0x000000B1, /* EMIF1_EXT_PHY_CTRL_30 */
0x00000048, /* EMIF1_EXT_PHY_CTRL_31 */
0x00000048, /* EMIF1_EXT_PHY_CTRL_32 */
0x00000049, /* EMIF1_EXT_PHY_CTRL_33 */
0x00000050, /* EMIF1_EXT_PHY_CTRL_34 */
0x0000004D, /* EMIF1_EXT_PHY_CTRL_35 */
0x00000077 /* EMIF1_EXT_PHY_CTRL_36 */
};
/* Changes for DDR ends here - Anupama */
static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
.dmm_lisa_map_3 = 0x80740300,
.is_ma_present = 0x1
};
static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
.dmm_lisa_map_3 = 0x80640100,
.is_ma_present = 0x1
};
static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
.dmm_lisa_map_2 = 0xc0600200,
.dmm_lisa_map_3 = 0x80600100,
.is_ma_present = 0x1
};
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
if (board_is_am571x_idk())
/* *dmm_lisa_regs = &am571x_idk_lisa_regs;*/ /* Commented by Anupama for DDR changes */
*dmm_lisa_regs = &AM571x_DDR3L_666MHz_TI_AM571x_IDK_dmm_regs; /* Added for DDR changes- Anupama */
else if (board_is_am574x_idk())
*dmm_lisa_regs = &am574x_idk_lisa_regs;
else
*dmm_lisa_regs = &beagle_x15_lisa_regs;
}
static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851b32,
.sdram_config = 0x61851b32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xcccf36ab,
.sdram_tim2 = 0x308f7fda,
.sdram_tim3 = 0x409f88a8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400b,
.emif_ddr_phy_ctlr_1 = 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
/* Ext phy ctrl regs 1-35 */
static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
0x10040100,
0x00910091,
0x00950095,
0x009B009B,
0x009E009E,
0x00980098,
0x00340034,
0x00350035,
0x00340034,
0x00310031,
0x00340034,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x00480048,
0x004A004A,
0x00520052,
0x00550055,
0x00500050,
0x00000000,
0x00600020,
0x40011080,
0x08102040,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0
};
static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851b32,
.sdram_config = 0x61851b32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xcccf36b3,
.sdram_tim2 = 0x308f7fda,
.sdram_tim3 = 0x407f88a8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400b,
.emif_ddr_phy_ctlr_1 = 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
0x10040100,
0x00910091,
0x00950095,
0x009B009B,
0x009E009E,
0x00980098,
0x00340034,
0x00350035,
0x00340034,
0x00310031,
0x00340034,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x00480048,
0x004A004A,
0x00520052,
0x00550055,
0x00500050,
0x00000000,
0x00600020,
0x40011080,
0x08102040,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0
};
static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
.sdram_config_init = 0x61863332,
.sdram_config = 0x61863332,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x0000514d,
.ref_ctrl_final = 0x0000144a,
.sdram_tim1 = 0xd333887c,
.sdram_tim2 = 0x30b37fe3,
.sdram_tim3 = 0x409f8ad8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400f,
.emif_ddr_phy_ctlr_1 = 0x0e24400f,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
.sdram_config_init = 0x61863332,
.sdram_config = 0x61863332,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x0000514d,
.ref_ctrl_final = 0x0000144a,
.sdram_tim1 = 0xd333887c,
.sdram_tim2 = 0x30b37fe3,
.sdram_tim3 = 0x409f8ad8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400f,
.emif_ddr_phy_ctlr_1 = 0x0e24400f,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305,
.emif_ecc_ctrl_reg = 0xD0000001,
.emif_ecc_address_range_1 = 0x3FFF0000,
.emif_ecc_address_range_2 = 0x00000000
};
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
switch (emif_nr) {
case 1:
if (board_is_am571x_idk())
/* *regs = &am571x_emif1_ddr3_666mhz_emif_regs; */ /* Commented by Anupama for DDR change */
*regs = &AM571x_DDR3L_666MHz_TI_AM571x_IDK_emif_regs; /* Added by Anupama for DDR change */
else if (board_is_am574x_idk())
*regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
else
*regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
break;
case 2:
if (board_is_am574x_idk())
*regs = &am571x_emif1_ddr3_666mhz_emif_regs;
else
*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
break;
}
}
void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
{
switch (emif_nr) {
case 1:
/*
*regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
*size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
*/ /* Commented by Anupam for DDR change */
*regs = AM571x_DDR3L_666MHz_TI_AM571x_IDK_emif1_ext_phy_regs;
*size = ARRAY_SIZE(AM571x_DDR3L_666MHz_TI_AM571x_IDK_emif1_ext_phy_regs);
break;
case 2:
*regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
*size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
break;
}
}
struct vcores_data beagle_x15_volts = {
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
.eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS45,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS6,
.core.pmic = &tps659038,
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
.iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS45,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
struct vcores_data am572x_idk_volts = {
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
.eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
.iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
struct vcores_data am571x_idk_volts = {
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
.eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
.iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS45,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
int get_voltrail_opp(int rail_offset)
{
int opp;
switch (rail_offset) {
case VOLT_MPU:
opp = DRA7_MPU_OPP;
break;
case VOLT_CORE:
opp = DRA7_CORE_OPP;
break;
case VOLT_GPU:
opp = DRA7_GPU_OPP;
break;
case VOLT_EVE:
opp = DRA7_DSPEVE_OPP;
break;
case VOLT_IVA:
opp = DRA7_IVA_OPP;
break;
default:
opp = OPP_NOM;
}
return opp;
}
#ifdef CONFIG_SPL_BUILD
/* No env to setup for SPL */
static inline void setup_board_eeprom_env(void) { }
/* Override function to read eeprom information */
void do_board_detect(void)
{
int rc;
rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS);
if (rc)
printf("ti_i2c_eeprom_init failed %d\n", rc);
}
#else /* CONFIG_SPL_BUILD */
/* Override function to read eeprom information: actual i2c read done by SPL*/
void do_board_detect(void)
{
char *bname = NULL;
int rc;
rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS);
if (rc)
printf("ti_i2c_eeprom_init failed %d\n", rc);
if (board_is_x15())
bname = "BeagleBoard X15";
else if (board_is_am572x_evm())
bname = "AM572x EVM";
else if (board_is_am574x_idk())
bname = "AM574x IDK";
else if (board_is_am572x_idk())
bname = "AM572x IDK";
else if (board_is_am571x_idk())
bname = "AM571x IDK";
if (bname)
snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
"Board: %s REV %s\n", bname, board_ti_get_rev());
}
static void setup_board_eeprom_env(void)
{
char *name = "beagle_x15";
int rc;
rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS);
if (rc)
goto invalid_eeprom;
if (board_is_x15()) {
if (board_is_x15_revb1())
name = "beagle_x15_revb1";
else if (board_is_x15_revc())
name = "beagle_x15_revc";
else
name = "beagle_x15";
} else if (board_is_am572x_evm()) {
if (board_is_am572x_evm_reva3())
name = "am57xx_evm_reva3";
else
name = "am57xx_evm";
} else if (board_is_am574x_idk()) {
name = "am574x_idk";
} else if (board_is_am572x_idk()) {
name = "am572x_idk";
} else if (board_is_am571x_idk()) {
name = "am571x_idk";
} else {
printf("Unidentified board claims %s in eeprom header\n",
board_ti_get_name());
}
invalid_eeprom:
set_board_info_env(name);
}
#endif /* CONFIG_SPL_BUILD */
void vcores_init(void)
{
if (board_is_am572x_idk() || board_is_am574x_idk())
*omap_vcores = &am572x_idk_volts;
else if (board_is_am571x_idk())
*omap_vcores = &am571x_idk_volts;
else
*omap_vcores = &beagle_x15_volts;
}
void hw_data_init(void)
{
*prcm = &dra7xx_prcm;
if (is_dra72x())
*dplls_data = &dra72x_dplls;
else if (is_dra76x())
*dplls_data = &dra76x_dplls;
else
*dplls_data = &dra7xx_dplls;
*ctrl = &dra7xx_ctrl;
}
bool am571x_idk_needs_lcd(void)
{
bool needs_lcd;
needs_lcd = false;
return needs_lcd;
#if 0
gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
if (gpio_get_value(GPIO_ETH_LCD))
needs_lcd = false;
else
needs_lcd = true;
gpio_free(GPIO_ETH_LCD);
return needs_lcd;
#endif
}
int board_init(void)
{
gpmc_init();
gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
return 0;
}
void am57x_idk_lcd_detect(void)
{
int r = -ENODEV;
char *idk_lcd = "no";
uint8_t buf = 0;
/* Only valid for IDKs */
if (board_is_x15() || board_is_am572x_evm())
return;
/* Only AM571x IDK has gpio control detect.. so check that */
if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
goto out;
r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
if (r) {
printf("%s: Failed to set bus address to %d: %d\n",
__func__, OSD_TS_FT_BUS_ADDRESS, r);
goto out;
}
r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
if (r) {
/* AM572x IDK has no explicit settings for optional LCD kit */
if (board_is_am571x_idk()) {
printf("%s: Touch screen detect failed: %d!\n",
__func__, r);
}
goto out;
}
/* Read FT ID */
r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
if (r) {
printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
__func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
OSD_TS_FT_REG_ID, r);
goto out;
}
switch (buf) {
case OSD_TS_FT_ID_5606:
idk_lcd = "osd101t2045";
break;
case OSD_TS_FT_ID_5x46:
idk_lcd = "osd101t2587";
break;
default:
printf("%s: Unidentifed Touch screen ID 0x%02x\n",
__func__, buf);
/* we will let default be "no lcd" */
}
out:
env_set("idk_lcd", idk_lcd);
/*
* On AM571x_IDK, no Display with J51 set to LCD is considered as an
* invalid configuration and we prevent boot to get user attention.
*/
if (board_is_am571x_idk() && am571x_idk_needs_lcd() &&
!strncmp(idk_lcd, "no", 2)) {
printf("%s: Invalid HW configuration: display not detected/supported but J51 is set. Remove J51 to boot without display.\n",
__func__);
hang();
}
return;
}
#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
static int device_okay(const char *path)
{
int node;
node = fdt_path_offset(gd->fdt_blob, path);
if (node < 0)
return 0;
return fdtdec_get_is_enabled(gd->fdt_blob, node);
}
#endif
int board_late_init(void)
{
setup_board_eeprom_env();
u8 val;
/*
* DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
* This is the POWERHOLD-in-Low behavior.
*/
palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
/*
* Default FIT boot on HS devices. Non FIT images are not allowed
* on HS devices.
*/
if (get_device_type() == HS_DEVICE)
env_set("boot_fit", "1");
/*
* Set the GPIO7 Pad to POWERHOLD. This has higher priority
* over DEV_CTRL.DEV_ON bit. This can be reset in case of
* PMIC Power off. So to be on the safer side set it back
* to POWERHOLD mode irrespective of the current state.
*/
palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
&val);
val = val | TPS65903X_PAD2_POWERHOLD_MASK;
palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
val);
omap_die_id_serial();
omap_set_fastboot_vars();
am57x_idk_lcd_detect();
#if !defined(CONFIG_SPL_BUILD)
board_ti_set_ethaddr(2);
#endif
#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
if (device_okay("/ocp/omap_dwc3_1@48880000"))
enable_usb_clocks(0);
if (device_okay("/ocp/omap_dwc3_2@488c0000"))
enable_usb_clocks(1);
#endif
return 0;
}
void set_muxconf_regs(void)
{
do_set_mux32((*ctrl)->control_padconf_core_base,
early_padconf, ARRAY_SIZE(early_padconf));
}
#ifdef CONFIG_IODELAY_RECALIBRATION
void recalibrate_iodelay(void)
{
const struct pad_conf_entry *pconf;
const struct iodelay_cfg_entry *iod, *delta_iod;
int pconf_sz, iod_sz, delta_iod_sz = 0;
int ret;
if (board_is_am572x_idk()) {
pconf = core_padconf_array_essential_am572x_idk;
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
iod = iodelay_cfg_array_am572x_idk;
iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
} else if (board_is_am574x_idk()) {
pconf = core_padconf_array_essential_am574x_idk;
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
iod = iodelay_cfg_array_am574x_idk;
iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
} else if (board_is_am571x_idk()) {
pconf = core_padconf_array_essential_am571x_idk;
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
iod = iodelay_cfg_array_am571x_idk;
iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
} else {
/* Common for X15/GPEVM */
pconf = core_padconf_array_essential_x15;
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
/* There never was an SR1.0 X15.. So.. */
if (omap_revision() == DRA752_ES1_1) {
iod = iodelay_cfg_array_x15_sr1_1;
iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
} else {
/* Since full production should switch to SR2.0 */
iod = iodelay_cfg_array_x15_sr2_0;
iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
}
}
/* Setup I/O isolation */
ret = __recalibrate_iodelay_start();
if (ret)
goto err;
/* Do the muxing here */
do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
/* Now do the weird minor deltas that should be safe */
if (board_is_x15() || board_is_am572x_evm()) {
if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
board_is_x15_revc()) {
pconf = core_padconf_array_delta_x15_sr2_0;
pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
} else {
pconf = core_padconf_array_delta_x15_sr1_1;
pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
}
do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
}
if (board_is_am571x_idk()) {
if (am571x_idk_needs_lcd()) {
pconf = core_padconf_array_vout_am571x_idk;
pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
delta_iod = iodelay_cfg_array_am571x_idk_4port;
delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
} else {
pconf = core_padconf_array_icss1eth_am571x_idk;
pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
}
do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
}
/* Setup IOdelay configuration */
ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
if (delta_iod_sz)
ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
delta_iod_sz);
err:
/* Closeup.. remove isolation */
__recalibrate_iodelay_end(ret);
}
#endif
#if defined(CONFIG_MMC)
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0, 0, 0, -1, -1);
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
.hw_rev = "rev11",
.unsupported_caps = MMC_CAP(MMC_HS_200) |
MMC_CAP(UHS_SDR104),
.max_freq = 96000000,
};
static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
.hw_rev = "rev11",
.unsupported_caps = MMC_CAP(MMC_HS_200) |
MMC_CAP(UHS_SDR104) |
MMC_CAP(UHS_SDR50),
.max_freq = 48000000,
};
const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
{
switch (omap_revision()) {
case DRA752_ES1_0:
case DRA752_ES1_1:
if (addr == OMAP_HSMMC1_BASE)
return &am57x_es1_1_mmc1_fixups;
else
return &am57x_es1_1_mmc23_fixups;
default:
return NULL;
}
}
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
#ifdef CONFIG_SPL_ENV_SUPPORT
env_init();
env_load();
if (env_get_yesno("boot_os") != 1)
return 1;
#endif
return 0;
}
#endif
#ifdef CONFIG_USB_DWC3
static struct dwc3_device usb_otg_ss2 = {
.maximum_speed = USB_SPEED_HIGH,
.base = DRA7_USB_OTG_SS2_BASE,
.tx_fifo_resize = false,
.index = 1,
};
static struct dwc3_omap_device usb_otg_ss2_glue = {
.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
.index = 1,
};
static struct ti_usb_phy_device usb_phy2_device = {
.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
.index = 1,
};
int usb_gadget_handle_interrupts(int index)
{
u32 status;
status = dwc3_omap_uboot_interrupt_status(index);
if (status)
dwc3_uboot_handle_interrupt(index);
return 0;
}
#endif /* CONFIG_USB_DWC3 */
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
int board_usb_init(int index, enum usb_init_type init)
{
enable_usb_clocks(index);
switch (index) {
case 0:
if (init == USB_INIT_DEVICE) {
printf("port %d can't be used as device\n", index);
disable_usb_clocks(index);
return -EINVAL;
}
break;
case 1:
if (init == USB_INIT_DEVICE) {
#ifdef CONFIG_USB_DWC3
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
ti_usb_phy_uboot_init(&usb_phy2_device);
dwc3_omap_uboot_init(&usb_otg_ss2_glue);
dwc3_uboot_init(&usb_otg_ss2);
#endif
} else {
printf("port %d can't be used as host\n", index);
disable_usb_clocks(index);
return -EINVAL;
}
break;
default:
printf("Invalid Controller Index\n");
}
return 0;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
#ifdef CONFIG_USB_DWC3
switch (index) {
case 0:
case 1:
if (init == USB_INIT_DEVICE) {
ti_usb_phy_uboot_exit(index);
dwc3_uboot_exit(index);
dwc3_omap_uboot_exit(index);
}
break;
default:
printf("Invalid Controller Index\n");
}
#endif
disable_usb_clocks(index);
return 0;
}
#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
#ifdef CONFIG_DRIVER_TI_CPSW
/* Delay value to add to calibrated value */
#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
static void cpsw_control(int enabled)
{
/* VTP can be added here */
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 1,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 2,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
static u64 mac_to_u64(u8 mac[6])
{
int i;
u64 addr = 0;
for (i = 0; i < 6; i++) {
addr <<= 8;
addr |= mac[i];
}
return addr;
}
static void u64_to_mac(u64 addr, u8 mac[6])
{
mac[5] = addr;
mac[4] = addr >> 8;
mac[3] = addr >> 16;
mac[2] = addr >> 24;
mac[1] = addr >> 32;
mac[0] = addr >> 40;
}
int board_eth_init(bd_t *bis)
{
int ret;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
uint32_t ctrl_val;
int i;
u64 mac1, mac2;
u8 mac_addr1[6], mac_addr2[6];
int num_macs;
/* try reading mac address from efuse */
mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = mac_hi & 0xFF;
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
mac_addr[5] = mac_lo & 0xFF;
if (!env_get("ethaddr")) {
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
}
mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = mac_hi & 0xFF;
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
mac_addr[5] = mac_lo & 0xFF;
if (!env_get("eth1addr")) {
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("eth1addr", mac_addr);
}
ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
ctrl_val |= 0x22;
writel(ctrl_val, (*ctrl)->control_core_control_io1);
/* The phy address for the AM57xx IDK are different than x15 */
if (board_is_am572x_idk() || board_is_am571x_idk() ||
board_is_am574x_idk()) {
cpsw_data.slave_data[0].phy_addr = 0;
cpsw_data.slave_data[1].phy_addr = 1;
}
ret = cpsw_register(&cpsw_data);
if (ret < 0)
printf("Error %d registering CPSW switch\n", ret);
/*
* Export any Ethernet MAC addresses from EEPROM.
* On AM57xx the 2 MAC addresses define the address range
*/
board_ti_get_eth_mac_addr(0, mac_addr1);
board_ti_get_eth_mac_addr(1, mac_addr2);
if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
mac1 = mac_to_u64(mac_addr1);
mac2 = mac_to_u64(mac_addr2);
/* must contain an address range */
num_macs = mac2 - mac1 + 1;
/* <= 50 to protect against user programming error */
if (num_macs > 0 && num_macs <= 50) {
for (i = 0; i < num_macs; i++) {
u64_to_mac(mac1 + i, mac_addr);
if (is_valid_ethaddr(mac_addr)) {
eth_env_set_enetaddr_by_index("eth",
i + 2,
mac_addr);
}
}
}
}
return ret;
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
/* VTT regulator enable */
static inline void vtt_regulator_enable(void)
{
if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
return;
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
int board_early_init_f(void)
{
vtt_regulator_enable();
return 0;
}
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (board_is_x15()) {
if (board_is_x15_revb1()) {
if (!strcmp(name, "am57xx-beagle-x15-revb1"))
return 0;
} else if (board_is_x15_revc()) {
if (!strcmp(name, "am57xx-beagle-x15-revc"))
return 0;
} else if (!strcmp(name, "am57xx-beagle-x15")) {
return 0;
}
} else if (board_is_am572x_evm() &&
!strcmp(name, "am57xx-beagle-x15")) {
return 0;
} else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
return 0;
} else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
return 0;
} else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
return 0;
}
return -1;
}
#endif
#ifdef CONFIG_TI_SECURE_DEVICE
void board_fit_image_post_process(void **p_image, size_t *p_size)
{
secure_boot_verify_image(p_image, p_size);
}
void board_tee_image_process(ulong tee_image, size_t tee_size)
{
secure_tee_install((u32)tee_image);
}
U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
#endif
We are trying to boot from sd-card, booting stops at the point "Starting kernel ..."
printenv and booting logs are attached.
We have done ddr test 0x80000000 0xbdf15d00 from u-boot prompt and it shows that test passed.
-------------
U-Boot 2018.01 (Feb 03 2020 - 11:22:17 +0530)
CPU : DRA722-GP ES2.0
Model: TI AM5718 IDK
Board: AM571x IDK REV 1.3B
DRAM: 1 GiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
Card did not respond to voltage select!
*** Warning - MMC init failed, using default environment
Card did not respond to voltage select!
invalid mmc device
SCSI: SATA link 0 timeout.
AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst
scanning bus for devices...
Found 0 device(s).
Net: Could not get PHY for ethernet@48484000: addr 0
Warning: ethernet@48484000 using MAC address from ROM
eth0: ethernet@48484000
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
** Unable to read file boot.scr **
1490 bytes read in 2 ms (727.5 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc0 ...
Running uenvcmd ...
1 bytes read in 2 ms (0 Bytes/s)
Already setup.
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
4026880 bytes read in 290 ms (13.2 MiB/s)
97137 bytes read in 56 ms (1.7 MiB/s)
## Flattened Device Tree blob at 88000000
Booting using the fdt blob at 0x88000000
Loading Device Tree to 8ffe5000, end 8ffffb70 ... OK
Starting kernel ...
-------------------------------------------
Can you give any suggestions to proceed ?
regards,
Anupama
