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Original question:

RTOS/PROCESSOR-SDK-AM335X: PRU initialization issue

CCS/PROCESSOR-SDK-AM335X: Data abort exception

Shubham Shandilya22
Prodigy 705 points

Part Number: PROCESSOR-SDK-AM335X
Other Parts Discussed in Thread: SYSBIOS

Tool/software: Code Composer Studio

I am running my program on AM335x and i am running into data abort exception.

I see "CortxA8: Unhandled ADP_Stopped exception 0x20023" on my console when exception occurs and the ROV looks like below

MMU configuration in the .cfg file looks like below

/***********************************************
* MMU Configuration *
***********************************************/
var Mmu = xdc.useModule('ti.sysbios.family.arm.a8.Mmu');
Mmu.enableMMU = true;

var peripheralAttrs = {
type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
tex: 1,
bufferable : true, // bufferable
cacheable : true, // cacheable
shareable : false, // shareable
noexecute : false, // not executable
};

/* MMU configuration for NOR - bufferable| Cacheable */
var peripheralBaseAddr = 0x08000000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

/* MMU configuration for NOR - bufferable| Cacheable */
var peripheralBaseAddr = 0x08100000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

/* MMU configuration for NOR - bufferable| Cacheable */
var peripheralBaseAddr = 0x08200000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);


/* Force peripheral section to be NON cacheable strongly-ordered memory */
var peripheralAttrs = {
type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
tex: 0,
bufferable : false, // bufferable
cacheable : false, // cacheable
shareable : false, // shareable
noexecute : false, // not executable
};

/* MMU configuration for PWM - Non bufferable| Non Cacheable */
var peripheralBaseAddr = 0x48300000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

/* MMU configuration for INTCPS,MPUSS - Non Bufferable| Non Cacheable */
var peripheralBaseAddr = 0x48200000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

/* MMU configuration for I2C2,McSPI1,UART3,UART4,UART5, GPIO2,GPIO3,MMC1 - Non bufferable| Non Cacheable */
var peripheralBaseAddr = 0x48100000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

/* MMU configuration for UART1,UART2,I2C1,McSPI0,McASP0 CFG,McASP1 CFG,DMTIMER,GPIO1 -Non bufferable| Non Cacheable */
var peripheralBaseAddr = 0x48000000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

/* MMU configuration for UART1,UART2,I2C1,McSPI0,McASP0 CFG,McASP1 CFG,DMTIMER,GPIO1 -Non bufferable| Non Cacheable */
var peripheralBaseAddr = 0x48030000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

/* MMU configuration for Clock Module, PRM, GPIO0, UART0, I2C0, - Non bufferable| Non Cacheable */
var peripheralBaseAddr = 0x44E00000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);


var peripheralAttrs = {
type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
tex: 1,
bufferable : true, // bufferable
cacheable : false, // cacheable
shareable : true, // shareable
noexecute : false, // not executable
};

/* MMU configuration for //PRUSS1 -Bufferable| Non Cacheable | Shareable */
var peripheralBaseAddr = 0x4A300000; // Should it be bufferable??
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);


var peripheralAttrs = {
type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
tex: 0,
bufferable : false, // bufferable
cacheable : false, // cacheable
shareable : false, // shareable
noexecute : false, // not executable
};

/* MMU configuration for EDMA3 - Non bufferable| Non Cacheable */
var peripheralBaseAddr = 0x49000000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

/* MMU configuration for L4 FAST CFG- Non bufferable| Non Cacheable */
var peripheralBaseAddr = 0x4A000000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

/* MMU configuration for CPSW - Non bufferable| Non Cacheable */
var peripheralBaseAddr = 0x4A100000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

var peripheralBaseAddr = 0x49a00000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

var peripheralBaseAddr = 0x49900000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

var peripheralBaseAddr = 0x49800000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

var peripheralBaseAddr = 0x40300000;
Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

can anyone help me on what could be causing this data abort and how to  resolve this?

  • 0
    TI__Mastermind 30098 points

    Hi Shubham,

    Please see DDI0344K_cortex_a8_r3p2_trm.pdf, Section 2.15.1 Exception entry and exit summary.

    In your ROV snapshot, it appears R14_abt (lr) contains 0x4a303e58. This is an address in PRU_ICSS DMEM1, so I believe a read/write to DMEM1 caused the data abort.

    Can you please try the MMU settings contained in the file pdk_am57xx_1_0_16\packages\ti\drv\uart\test\firmware_test\am335x\armv7\bios\am335x_app_bbbam335x.cfg (see below) and let me know the outcome?

    /* Force peripheral section to be NON cacheable strongly-ordered memory */
    var peripheralAttrs = {
        type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
        tex: 0,
        bufferable : false, // bufferable
        cacheable : false, // cacheable
        shareable : false, // shareable
        noexecute : true, // not executable
        domain : 0,
        imp : 1,
        accPerm : 3,
    };

    /* Define the base address of the 1 Meg page the peripheral resides in. */
    var peripheralBaseAddr = 0x4a300000;

    /* Configure the corresponding MMU page descriptor accordingly */
    Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
    peripheralBaseAddr,
    peripheralAttrs);

    Thanks and regards,
    Frank

     

  • 0 in reply to Frank Livingston
    TI__Prodigy 705 points

    Franks,

    Thanks for your reply.

    I tried the MMU setting that you have suggested.

    I see the same issue with the new settings.

  • 0 in reply to Shubham Shandilya22
    TI__Prodigy 705 points

    some more details i see on console after enabling sysmin buffer

    [CortxA8] 0 PC(R15) = 0x8005e848
    PSR = 0x6000019f
    DFSR = 0x00000005 IFSR = 0x00000000
    DFAR = 0x00000000 IFAR = 0x00000000
    ti.sysbios.family.arm.exc.Exception: line 205: E_dataAbort: pc = 0x8005e848, lr = 0x4a303e58.
    xdc.runtime.Error.raise: terminating execution

    cortex A8 trm suggests that DFSR = 0x00000005 points to 

    DFSR - > b000101 -> translation fault, section

    i am not sure what exactly it means.

  • 0 in reply to Shubham Shandilya22
    TI__Prodigy 705 points

    This is resolved now.

    The issue was due to library wasn't built correctly.

    One of the structure definition was changed in library header file after library was built, leading to mismatch of structure definition between the library and application.

    Thanks frank for taking time to respond and guiding in right direction.