Hello,
The communication between AM5726 and an another processor with async NOR interface there are some timing problems on read cycle.
I have set up the longest timings on read for the AM5726. GPMC controller but its not enough. It is possible to lower the clock GPMC_FCLK?
Best Regards
Part Number: AM5726
Hello,
(this thread isnt solved)
The communication between AM5726 and an another processor with async NOR interface there are some timing problems on read cycle.
If I read 32k data, 30k of it has been read correctly. I think the GPMC-controller reads to fast the data. When i look at the data, then i notice that often the upper 4 bits have the same values as the lower bits. or that the next byte has the same values as the previous byte in the upper part.
I would like the access to the data just before cs0 gets high.
How can I further delay data access so that it is always guaranteed that the data is accessed at the right time?
Here is the GPMC config:
#define GPMC_REG_VAL_WAIT1PINPOLARITY 0x00 /* 0 - 1 */ #define GPMC_REG_VAL_WAIT0PINPOLARITY 0x00 /* 0 - 1 */ #define GPMC_REG_VAL_WRITEPROTECT 0x00 /* 0 - 1 .. Reserved */ #define GPMC_REG_VAL_LIMITEDADDRESS 0x00 /* 0 - 1 .. Reserved */ #define GPMC_REG_VAL_NANDFORCEPOSTEDWRITE 0x00 /* 0 - 1 */ /* REG CONFIG1 */ #define GPMC_REG_VAL_WRAPBURST 0x00 /* 0 - 1 */ #define GPMC_REG_VAL_READMULTIPLE 0x00 /* 0 - 1 */ #define GPMC_REG_VAL_READTYPE 0x00 /* 0 - 1 */ #define GPMC_REG_VAL_WRITEMULTIPLE 0x00 /* 0 - 1 */ #define GPMC_REG_VAL_WRITETYPE 0x00 /* 0 - 1 */ #define GPMC_REG_VAL_CLKACTIVATIONTIME 0x00 /* 0 - 2 */ #define GPMC_REG_VAL_ATTACHEDDEVICEPAGELENGTH 0x00 /* 0 - 2 */ #define GPMC_REG_VAL_WAITREADMONITORING 0x01 /* 0 - 1 */ #define GPMC_REG_VAL_WAITWRITEMONITORING 0x00 /* 0 - 1 */ #define GPMC_REG_VAL_WAITONMONITORINGTIME 0x00 /* 0 - 2 */ #define GPMC_REG_VAL_WAITPINSELECT 0x00 /* 0 - 1 */ #define GPMC_REG_VAL_DEVICESIZE 0x01 /* 0 - 1 */ #define GPMC_REG_VAL_DEVICETYPE 0x00 /* 0, 2 */ #define GPMC_REG_VAL_MUXADDATA 0x00 /* 0 - 2 */ #define GPMC_REG_VAL_TIMEPARAGRANULARITY 0x01 /* 0 - 1 */ #define GPMC_REG_VAL_GPMCFCLKDIVIDER 0x03 /* 0 - 3 */ /* REG CONFIG2 */ #define GPMC_REG_VAL_CSWROFFTIME 0x10 /* 0 - 1F */ #define GPMC_REG_VAL_CSRDOFFTIME 0x1f /* 0 - 1F */ #define GPMC_REG_VAL_CSEXTRADELAY 0x01 /* 0 - 1 */ #define GPMC_REG_VAL_CSONTIME 0x00 /* 0 - 1F */ /* REG CONFIG3 */ #define GPMC_REG_VAL_ADVAADMUXWROFFTIME 0x02 /* 0 - 7 */ #define GPMC_REG_VAL_ADVAADMUXRDOFFTIME 0x02 /* 0 - 7 */ #define GPMC_REG_VAL_ADVWROFFTIME 0x06 /* 0 - 1F */ #define GPMC_REG_VAL_ADVRDOFFTIME 0x05 /* 0 - 1F */ #define GPMC_REG_VAL_ADVEXTRADELAY 0x00 /* 0 - 1 */ #define GPMC_REG_VAL_ADVAADMUXONTIME 0x01 /* 0 - 9 */ #define GPMC_REG_VAL_ADVONTIME 0x04 /* 0 - F */ /* REG 4 */ #define GPMC_REG_VAL_WEOFFTIME 0x10 /* 0 - 1F */ #define GPMC_REG_VAL_WEEXTRADELAY 0x01 /* 0 - 1 */ #define GPMC_REG_VAL_WEONTIME 0x05 /* 0 - F */ #define GPMC_REG_VAL_OEAADMUXOFFTIME 0x03 /* 0 - 7 */ #define GPMC_REG_VAL_OEOFFTIME 0x1f /* 0 - 1F */ #define GPMC_REG_VAL_OEEXTRADELAY 0x01 /* 0 - 1 */ #define GPMC_REG_VAL_OEAADMUXONTIME 0x01 /* 0 - 7 */ #define GPMC_REG_VAL_OEONTIME 0x00 /* 0 - F */ /* REG 5 */ #define GPMC_REG_VAL_RDACCESSTIME 0x1e /* 0 - 1F */ #define GPMC_REG_VAL_WRCYCLETIME 0x11 /* 0 - 1F */ #define GPMC_REG_VAL_RDCYCLETIME 0x1f /* 0 - 1F */ /* REG 6 */ #define GPMC_REG_VAL_WRACCESSTIME 0x0f /* 0 - 1F */ #define GPMC_REG_VAL_WRDATAONADMUXBUS 0x07 /* 0 - F */ #define GPMC_REG_VAL_CYCLE2CYCLEDELAY 0x0f /* 0 - F */ #define GPMC_REG_VAL_CYCLETOCYCLESAMECSEN 0x01 /* 0 - 1 */ #define GPMC_REG_VAL_CYCLE2CYCLEDIFFCSEN 0x01 /* 0 - 1 */ #define GPMC_REG_VAL_BUSTURNAROUND 0x04 /* 0 - F */ /* REG 7 for bank 0 */ #define GPMC_REG_VAL_MASKADDRESS 0x0F /* 0 - F */ #define GPMC_REG_VAL_CSVALID 0x01 /* 0 - 1 */ #define GPMC_REG_VAL_BASEADDRESS 0x08 /* 0 - 1F */
configure GPMC
GPMC_CONFIG_REG 0x00000000
GPMC_CONFIG_REG1_0 0x00401013
GPMC_CONFIG_REG2_0 0x00101f80
GPMC_CONFIG_REG3_0 0x22060514
GPMC_CONFIG_REG4_0 0x10857f90
GPMC_CONFIG5_0 0x001e111f
GPMC_CONFIG6_0 0x0f070fc4
GPMC_CONFIG7_0 0x00000f48
Look at the picture below, there is a screenshot from digital-analyzer. It is an async Read cycle. The time distance between cs0 and wait0 is 120 ns.
It looks fine, but I think the access to the data is "sometimes" too early.
0. (green) Chipselect0
1. (red) noe
2. (blue) wen
3. (brown) wait0/rdy
4/5. (yellow) Adress0 and Adress1
6/7. (light blue) Data0 and Data1
