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TMS320C6678: EVM REV 3_0 Known Issues

erez cohen
Intellectual 595 points
Part Number: TMS320C6678

Hello,

on Advantech document TMDSEVM6678Lx_EVM_REV_3_0
_Known_Issues.docx section 4.2.4 there are few notes:

1. DDRSLRATE[1:0] should be pulled up to 1.8V instead of 1.5V. is that confirmed?

2. DDRRESET# should pull up 2K to VCC1V8 rather than VTT. current schematics connect the 4.7K PU to 1.5V. what should be done?

thanks,

Erez.

  • 0
    TI__Mastermind 46460 points

    Erez,

    The statements in the Known issues document are correct.

    The DDRRESET# signal from the DSP is driven into the RESET# signal in the DRAMs.  The JEDEC spec defines this input as "a CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD". The design currently contains a 10K pull-up resistor to VTT. This termination does not impact operation but it is misleading. This signal should contain a weak pull-up 2k to VCC1V8 rather than to VTT.

    The DDRSLRATE[1:0] pins of the C6678 DSP are 1.8V LVCMOS inputs. The EVM design incorrectly pulls then to 1.5V (DVDD15). This is a non-critical issue that will be fixed if the board layout is revised in the future. The 1.5V input will always be above the Vih(min) of the 1.8V LVCMOS input. This issue will not cause the EVM to fail to operate properly but it does cause confusion. All customer designs should pull the DDRSLRATE[1:0] pins to either 1.8V or Ground.

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 595 points

    Tom,

    Regarding the DDRRESET# (Ball E11), it is written on SPRACLA9 (Schematic Checklist) P.7 the signal is LVCMOS using VDDQ levels and the signal MUST have Pull Down. i can not see the pull down on the Reference design. it is actually pulled up to 1.8V. what should be done? 

    Erez.

  • 0 in reply to erez cohen
    TI__Mastermind 46460 points

    Erez,

    Having a resistor to ground on this pin guarantees that the SDRAM is properly held in RESET after power-up when the DDRRESET# pin is HI-Z.  Once the DDR controller is initialized, the pin will be driven low and later high as part of the PHY and SDRAM initialization sequence.  The EVM does not follow this guidance since it pre-dated all customer documentation.  We designed the EVM to potentially support low power modes where the SDRAM could be put in self-refresh.  These modes may have required a reset to the C6678 as part of the wake-up process and we did not want this reset to wipe the SDRAM's contents.  We later decided not to productize that capability.  The schematic checklist contains the guidance that needs to be followed.

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 595 points

    Tom,

    thanks for your answer.

    in that case i will have 2K PD assembled instead of the PU.

    in addition on the checklist section 6.1.2 it says SerDes REFRES should be 3K 1% to GND. i couldn't see it on the DS pin description. 

    please advise if checklist overcomes the EVB schematics. I assume yes.

    Erez.

  • 0 in reply to erez cohen
    TI__Mastermind 46460 points

    Erez,

    Customer documentation such as data manuals / data sheets and design guides always contain the latest guidance.  The EVM design is an sample design that has features and options or perhaps deficiencies that may not be recommended for the average customer's design.

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 595 points

    Tom,

    On the checklist section 6.1.2 it says SerDes REFRES should be 3K 1% to GND. Where i can see it on the DS? What Ball is it refers?

    Erez. 

  • 0 in reply to erez cohen
    TI__Mastermind 46460 points

    Erez,

    The schematic checklist that you are using is for both KeyStone1 and KeyStone 2 devices.  The SERDES implementations are different between these 2 device families.  C6678 is a KS1 device.  Only KS2 devices have SERDES REFRES resistors.

    Tom