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TDA4VM: OSPI timing parameters

John H. Gardner
Guru 55591 points
Part Number: TDA4VM


Context: customer is using our OSPI interface to connect to a Micron OSPI flash (MT35XU512ABA)

Do we have timing parameters of OSPI, for TDA4VM, at higher operating frequency at DDR mode?  ( Micron OSPI memory can work at 200MHz )
Unfortunately in datasheet ther appears to only be timing parameters for DDR mode for OSPI for 50 MHz.  (page 241,  243, 244 in datasheet TDA4VM) (tables 5-89,5-91, Figure 5-89 and Figures 5-90)
Could you please send me the timing parameters,  which can meet NOR OSPI flash at 200MHz  - O13, O14, O15, O16, O17  and O18 ( page 244 in datasheet TDA4VM).

  • 0
    TI__Guru 55591 points

    Received the following response from hardware applications. They indicated that that they will "...be referring to page and table numbers from Datasheet Revision E (http://www.ti.com/lit/ds/symlink/tda4vm.pdf).  The numbers [the customer] cites are for 'no data training' operation.  That is, using the OSPI in PHY mode with fixed TX and RX delay values from Table 5-111 (Page 260).  As [the customer] correctly points out, 50MHz DDR is well below the capability of the target flash device.  In order to maximize performance, [the customer] has to tune the TX and RX delays using a tuning algorithm.  This is what the data sheet means by “Data Training.”  Table 5-106 (Page 256) gives the maximum speeds for the interface with data training, which is 166MHz DDR and 200MHz SDR.  The purpose of data training is to use the TX and RX delays to meet setup and hold timings.  Thus, the parameters tables 5-107 and 5-108 are not needed."

  • 0 in reply to John H. Gardner
    TI__Mastermind 42515 points

    Hi John,

    thanks for updating the thread.

    Regards,

    Yordan

  • 0 in reply to Yordan Kamenov
    TI__Guru 55591 points

    Two additional follow-up questions: 

    Some information is needed about the values in table 5-111: 

    1. Is this value  (circled in red above) automatically (after “data training”) placed on config register or need to put it manually?
    2.  0X45   corresponds to 1000101  which is  69 . Is this value corresponds to these 25% delay (from period) ,referred to stand point, as initial value.
          Is it maximum value, connected to delay, that I can put in this register. If yes, this means that for 200 MHz <> T = 5 ns <>  25% from period =1.25ns  and finally I can divide  1.25 / 69  to receive increment of delay. Could you please clarify? 

  • 0 in reply to John H. Gardner
    TI__Expert 4015 points

    My name is Zack, from Hardware Apps.  To answer your questions:

    1. The values circled above are not default values for the config register.  They need to put there by software.

    2. These are the number of delay elements to be put on the TX clock and DQS delay lines.  It is not 25% of a period.  To achieve these delays, the PHY must be configured in bypass mode, and the values 0x45 and 0x14 must be loaded into the register fields OSPI_PHY_CONFIGURATION_REG[22:16] and OSPI_PHY_CONFIGURATION_REG[6:0], respectively.  Also, for these settings (DDR mode, no data training) the maximum frequency is 50MHz, not 200MHz as your post implies.

  • 0 in reply to z
    TI__Guru 55591 points

    Zack,

    Thanks for the quick answer.  A couple additional:

    1. If I put controller in “data training mode”, how are stored the  values of these two registers ( for RX and TX) - [22:16] and  [6:0]-  automatically or manually?
     
    2. How many  “ns” is one delay element ?

    John

  • 0 in reply to John H. Gardner
    TI__Expert 4015 points

    Yordan,

    1. "Data training mode" is not a controller mode.   It simply refers to operation after performing the tuning procedure I mentioned earlier, which selects TX and RX delays to meet setup and hold timings of each system.  This contrasts to "no data training", which uses fixed delay values and can apply to all systems.  The tuning procedure is a manual process that must be done at startup.

    2.  This value can vary, but the nominal value is 50 picoseconds per delay element.

    -Zack