• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 97 subscribers
  • Views 409 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2H12: Cache_writeback internal mechanism

SamSeytani
Intellectual 535 points

Part Number: 66AK2H12

Hello all,

When I write some data to DDR3 memory from DSP, enabling L2_cache and after the transfer calling Cache_writeback has a higher throughput that direct access to DDR (without L2_cache). Why is this happening? Both methods should follow the same ways.

Best Regards.

  • 0
    TI__Guru* 95265 points

    Hi,

    When L2 cache is enabled, DDR is cached into L2. That is why CPU writing to DDR is faster when L2 cache is enabled vs L2 cache disabled.

    Regards, Eric

  • 0 in reply to lding
    Intellectual 535 points

    But cached version does a writeback. If there is a writeback should it not be the same as non-cached version?

  • 0 in reply to SamSeytani
    TI__Guru* 95265 points

    Hi,

    I am not sure how you measure the throughput. If you just use one core, you don't need to do the cache_writeback, unless your purpose is to use another master to access the data.

    Regards, Eric 

  • 0 in reply to lding
    Intellectual 535 points

    I want the data to be written to DDR. My measurement requires the data to be written back. Is it possible that cache_writeback uses some kind of DMA?

  • 0 in reply to SamSeytani
    TI__Guru* 95265 points

    Hi,

    If you want to write data from L2 to DDR3

    • Method 1: use EDMA, the EDMA has an IPR register to indicate the write finished. If your CPU wants to use the data in DDR, you need a cache_invalidate.
    • Method 2: use CPU like memcpy(), the function returns when the copy finished. If the same CPU A wants to use the data in DDR, you don't need cache operation. If another CPU B wants to use the data, CPU A needs a cache invalidate and writeback. then CPU B needs a cache invalidate.

    Cache operation is writing to some registers defined in C66x corepac, this is not a DMA style operation. Those registers are not accessible by EDMA.

    Regards, Eric 


     

  • 0 in reply to lding
    Intellectual 535 points

    To be clarify further, when I call cache writeback L2 cache fully for example, how is it written to DDR? Is it using 64 bit transfers as CPUs store double word instruction or something else? I need to be sure about it.

    Regards.

  • 0 in reply to SamSeytani
    TI__Guru* 95265 points

    Hi,

    • L2 cache line is 128 bytes, that is 1024 bit.
    • DSP VBUS is 256 bit. 
    • The DDR3A EMIF bus is 72-bit (64-bit data + 8-bit ECC).  

    When c66x does cache line write back, the write back is issued by the L2 cache controller, which is 256b MDMA interface. So each cache line (128B) is written to DDR_EMIF through MSMC with 4 cycles. 

    DDR write merges in the DDR FIFO. DDR3 write (or read) is always 8 x width (that is 512 bit). So 128B cache line eviction will look like 2 DDR write bursts, pretty much back to back.

    Regards, Eric

  • 0 in reply to lding
    Intellectual 535 points

    Thank you for your answer,

    In addition to that, i have another question. When there is concurrent cache writebacks say from 8 cores at the same time, are they arbitrated on the MSMC boundary before placing in DDR FIFOS regarding their priorities?

    Also what is the operation frequency of the bus line between MDMA to MSMC and MSMC to DDR3A?

    I want to estimate the arrival sequence of the commands to DDR in this concurrent scenario by assigning different prioririties to cores.

    Regards.

  • 0 in reply to SamSeytani
    TI__Guru* 95265 points

    Hi,

    In addition to that, i have another question. When there is concurrent cache writebacks say from 8 cores at the same time, are they arbitrated on the MSMC boundary before placing in DDR FIFOS regarding their priorities? =======>Yes

    Also what is the operation frequency of the bus line between MDMA to MSMC and MSMC to DDR3A? ======>It is 1/2 of SYSCLK.

    Regards, Eric