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Dear Experts:
I am doing some tests on CPSW9G's RGMII and RMII, because our final hardware design requires both RGMII and RMII ports, so I want to figure out how to configure different modes on any CPSW9G ports.
I found that there is a unit test app in psdk_rtos_auto_j7_06_01_00_15/pdk/packages/ti/drv/cpsw/unit_test, and the gTestTaskCfg in psdk_rtos_auto_j7_06_01_00_15/pdk/packages/ti/drv/cpsw/unit_test/test_framework/cpsw_testconfig.h defines a simple switch logic test case which taskCfgId is TASK_CFG_ID_SWITCH_TEST, so I build the unit test app and load it througt CCS to run the CPSW9G switching test.
Two Gbps ports on GESI Expansion Board work well. But the 100Mbps port does not work, port link is fine, and the port LED blinks when packets go into the port, but no packet switched to other ports at all.
Below is the UART log:
GESI board detected
===============
CPSW Test Select
===============
Current/Default System Settings:
------------------------
Uart timemout : 10000 msec
Default Iteration count : 1
1: Manual testing (select specific test case to run)
s: System Settings
q: Quit
Enter Choice:
1
Manual testing
--------------------------------------
Select test to run as per below table:
--------------------------------------
1: CPSW9G Switching test
2: ALE auto learn test
3: ALE auto learn VLAN test
4: Mac speed test
5: Statistics test
6: VLAN test
8: CRC strip test
9: FIFO stats test
10: ALE source address update
11: ALE Table full
12: VLAN drop untagged
13: Multicast support
14: Policer test
15: Network security test
16: Host port Rx Filter
17: policer no match red drop enable test
18: policer no match yellow drop enable test
19: policer no match unregulated traffic test
20: Intervlan test
21: Default priority
22: Port VLAN ID
23: Sanity Test
24: Outer VLAN Test
25: Traffic shaping Test
26: 1-Gbps Full-Duplex Auto-Neg Test
27: 100-Mbps Full-Duplex Auto-Neg Test
28: 100-Mbps Half-Duplex Auto-Neg Test
29: DMA RxFlow Mtu Test
30: PHY Strap mode Test
31: Host sends 10 packets per VLAN PCP, PCP is inverted and switch priority is remapped
Enter Test to Run (Use UART1 console for all cores or MCU_UART1 console for MCU)
1
1
|TEST START|:: 1 ::
|TEST NAME| :: CPSW9G Switching test ::
|TEST INFO| :: Num Tasks : 1 ::
|TEST INFO| :: Data Check : Disabled ::
|TEST INFO| :: Profiling : Disabled ::
|TEST INFO| :: Print : Disabled ::
|TEST INFO| :: Run Instructions : To be added ::
|TEST ITEARATION NUMBER| :: : 1 ::
Enabling clocks for CPSW_9G!
CPSW_9G Test on MAIN NAVSS
CpswPhy_bindDriver: PHY 0: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
CpswPhy_bindDriver: PHY 3: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
CpswPhy_bindDriver: PHY 23: OUI:080028 Model:24 Ver:00 <-> 'generic' : OK
initQs() txFreePktInfoQ initialized with 1000 pkts
Host MAC address: 70:ff:76:1d:87:64
PHY 0 is alive
PHY 3 is alive
PHY 23 is alive
Waiting for PHY link on enabled ports mask:0x8C
Cpsw_isPortLinkUp: invalid layer 1
Cpsw_handleLinkUp: port 7: Link up: 100-Mbps Full-Duplex
MAC Port 7: link up
Cpsw_handleLinkUp: port 2: Link up: 1-Gpbs Full-Duplex
MAC Port 2: link up
