DSP BIOS 6.x RTSC support on the OMAP3530 Cortex A8 (CCSv4)

Rafael,

Thank you for your reply.  I downloaded and installed the updated tools as you recommended and was able to build a project based on the evm3530, which is exactly the platform that I'm using.

I tried the "list" example first, since it appeared to be the least complex of the examples.  However, when I built the project, i received the following build error:

/Program Files/Texas Instruments/ipc_1_00_05_60/packages/ti/sdo/utils/] was built with 'xdc.runtime' [2, 0, 0, 0, 1254957688197]  OMAP3530_BIOS6_configuration line 0 1294785395328 2217

Is it possible that I haven't configured the new xdctools properly, or are there some libraries that I need to update as well?

Thanks again for your help!

Bob

You should use at least the following versions which were first components to completely support A8.

XDC 3.20.0x
SYS/BIOS 6.31.0x
IPC 1.22.0x

You can get them here:

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/index.html

I'd recommend the latest in the series (patch releases with minor fixes) for each:

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/rtsc/3_20_06_81/index_FDS.html

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_31_02_23/index_FDS.html

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/1_22_01_21/index_FDS.html

Sorry.  Hit send too soon.  What version of CCS are you building with?   After installing new BIOS/IPC/XDC, you need to select them in the project manager. Looks like your error message references IPC 1.20.something which does not have A8 support.  You need 1.22.0x.

Bob,
I'd like to add some comments regarding IPC (interprocessor communication) support for OMAP3530.  The A8 core on OMAP3530 isn't supported by IPC, but OMAP3530/A8 is indeed supported by SYS/BIOS.  Attempting to use IPC modules with the A8 core on OMAP3530 should result in a build error.
However, IPC is not a dependency of SYS/BIOS (XDCTools is, however).  You should be able to build your application solely using SYS/BIOS and XDCTools.
Regards,
Shreyas

Karl/Rafael/Shreyas,

I was diverted from my efforts to get SysBios running by another project, so I'm just getting back to it.  I was able to build and link the SysBios Hello project, however, I need to change the DDR2 memory map slightly for my particular target.  I built a custom platform using the Tools->RTSC->Platform wizard, and it was saved in the default directory: C:\Documents and Settings\BobDavenport\myRepository\.  However, it isn't visible to my current project or new projects.  How do I attach the custom platform to a project?

Shreyas..

Thanks for the heads-up on IPC support.  I'm currently using a hand-coded IPC driver between the ARM and the C64x+, so hopefully that won't be an issue.  However, I'd like to use the TI IPC driver when it becomes available, so please keep me posted.

Thanks

Bob

Hi Bob,

You must update your CCS project build properties to specify the path to your custom platform.  The steps to do this may be found in the SYS/BIOS 6.x documentation:

Migrating a DSP/BIOS 5 Application to SYS/BIOS 6

(located in, for example, C:\Program Files\Texas Instruments\bios_6_30_02_42\docs\Bios_Legacy_App_Note.pdf)

Have a look under the section:

3.2 Updating a CCSv4 Project to Build with a Generated Platform Package

And then under step 4.

Hope this helps.

Steve

Steve,

There appears to be several useful documents in that sub-directory.   I'll go through the legacy app-note that you suggested as well as the "Getting Started' guide.  I may have been doing something wrong from the beginning.

Thanks for your help.

Bob

Steve,

I was able to attach my custom platform following the steps in Section 3.2 of the Migration app-note as you suggested.  However, it appears that my problem is unrelated to the platform.  When I attempted to load the new .out file, I received the following error message:

Cortex_A8_0: File Loader: Data verification failed at address 0x80F04000 Please verify target memory and memory map.

Error found during data verification.

Ensure the linker command file matches the memory map.

I received the same error message using the 3530evm platform, but the data verification error occurred at 0x80004000, so changing to the new memory map just moved the error higher.

I'm going to convert the Mailbox example using the Conversion Tool as described in the document and see how I make out.  In the meantime, I would appreciate any suggestions you might have.  (I'll also try distributing memory between the Cortex internal RAM and DDR2, to see if I can come up with a good combination).

Thanks

Bob

Bob,

It seems like you're doing everything correctly as far as the custom platform goes.  Are you using a GEL file?  If so, which one?

Also, can you please zip up and attach your *entire built* project?  Including the .out?

I'd like to have a look at it and see if I am able to load it here.  Also it will be easier for me to help if I can see what you've got so far.

Thanks,

Steve

Are you sure about your memory map?

This seems like a bootstrap problem. You can't load the code into memory until the memory is initialized.

In the CCS world, this issue is resolved by a GEL command that configures the memory prior to the user loading their code.

Alan

Steve/Alan,

I believe the problem is the target configuration for my Spectrum Digital XDS510-USB emulator.  When I upgraded my machine through the CCSv4 Update Link,  I also upgraded the Spectrum Digital drivers.  In CCS 4.1, there are three Spectrum Digital targets: an OMAP3530 EVM, a Mistral and a generic OMAP3530.  The Mistral target has GEL scripts that allow manual setting of the internal and external memory maps and the OMAP3530 EVM sets up the memory maps automatically when the device is connected.  The generic target only sets up the internal memory maps for the A8 and the C64x+ cores, which is the configuration that I see when I view the memory map of my SYS/BIOS program in CCS 4.2.

So I either need to write a GEL script to set up the external memory map or contact Spectrum Digital for a solution. I tried loading the program entirely in internal memory, but it exceeds the available memory.

Steve,

I zipped the project file, but I can't get it through the company firewall.  It is just the log example that was described in the literature you suggested and it built and linked OK.  I think the issue is probably the target configuration.

Thanks

Bob

Steve/Alan,

I found the GEL file that is currently being loaded by default (C:\Program Files\Texas Instruments\ccsv4\emulation\gel\omap3530_cortexA.gel), then renamed and replaced it with C:\Program Files\Texas Instruments\ccsv4\emulation\boards\omap35xx_3430\gel\Mistral_Omap35xx_CortexA8.gel.  That brought up the script that allowed me to set the A8 memory map and I was able to successfuly load and run the SYS/BIOS example on the A8 core.

Is there a way to modify the target configuration to look for a specific GEL file rather than renaming the file as I did?

Thanks

Bob

Shreyas,

Thanks for the information.  I'll configure the GEL file according to your suggestion.

After getting the A8 working, I investigated using SYS/BIOS on the C64x+ side.  I tried the same Log example but when I compile the project, I receive the following error:

>> Invalid intermediate file: C:\Program Files\Texas Instruments\bios_6_31_02_23\packages\ti\sysbios\timers\gptimer\lib\whole_program_debug\ti.sysbios.timers.gptimer.a64P, abortingerror: failed to recompile

I tried selecting earlier versions of SYSBIOS (6.30 and 6.21) and received different errors.  Any idea as to what the issue might be?

Thanks

Bob

Karl,

Please disregard my last post.  I was able to enable the new tools by recreating the project.  I am now able to develop and load SYS BIOS apps on both cores and co-emulated between the two.

SYS BIOS is going to be a helpful additon to our product and I would like to thank you, Rafael, Alan, Steve and Shreyas for your timely and helpful assistance.

Bob

Shreyas,

When you mentioned that IPC is not yet supported on the Cortex A8, did that include the RTSC Single Processor MessageQ project template?  I tried to build it on the A8 and received the following error message:

"C:/Program Files/Texas Instruments/ipc_1_21_02_23/packages/ti/sdo/ipc/gates/package.xs", line 82: Error: Library not found: ti.sdo.ipc.gates.anull

I searched the ipc lib directories and it looks like they primarily support DSP cores (e.g. ti.sdo.ip.gates.ae64p).  It appears that the Cortex M3 is the only ARM that is supported.

If this is the case, when is 1.32 going to be available?  If the C64x+ is supported, I'll use the example code on the DSP side of my project. However, I would ultimately like to use the same code on both cores.

Thanks

Bob

Bob,

I just fixed a typo in my earlier post--the IPC version that should support OMAP3530/A8 should be 1.23 and not 1.32.  To clarify IPC 1.21 (your version) does not support _any_ A8 targets which is why you are getting that particular build error.  IPC 1.22 introduces A8 support but only for certain devices (OMAP3530 is not one of them).  The reason A8 support for OMAP3530 was omitted is that most customers run an HLOS on the A8 (i.e. Linux).

IPC 1.23 with OMAP3530/A8 support could be available around March-April, but I cannot speculate on the exact date.

Regards,

Shreyas

Shreyas,

Thanks for your response.  After sending my post, I was able to get the Single Processor MessageQ example to work on the C64x+ core, so I assumed that it was not supported on the A8 as you confirmed.  I am able to get by with some hand-written buffer manager code, but the MessageQ will be much cleaner and will be portable between cores, so I'm looking forward to the release of 1.23.

Our final product is also using an HLOS.  I'm using SysBios as a means of testing interoperability between the two cores by co-emulating in two windows on CCSv4.  It save a lot of time and hardware.  Of course, SysBios could play a greater role in the future  with driver support for USB (USB to Ethernet) and serial interfaces (RS-232C for starters, followed by McBSP and McSPI).   Are there any DDK developments along those lines?

Thanks again,

Bob

We have no current plans to add BIOS support for USB and serial interfaces right now (this could change in the future, though). 

Regards,

Shreyas

Hello Everyone,

I am using beagleboard omap3530 with JTAG XDS100v2 on CCSv5.0.2.00006 version.

So, everything running fine, but when i am debugging the even simple hello world program it is showing me error, which i can see in the console window.

Error is something about memory map conflicts or settings.

Cortex_A8_0: GEL Output: OMAP 32K Watchdog Timer is disable

Cortex_A8_0: GEL Output: Putting DPLL into bypass before proceeding

Cortex_A8_0: GEL Output: Putting CORE DPLL into bypass before proceeding

Cortex_A8_0: GEL Output: Locking CORE DPLL

Cortex_A8_0: GEL Output: PRCM clock configuration IIA setup has been completed

Cortex_A8_0: GEL Output: SystemClock = 19.2 MHz

Cortex_A8_0: GEL Output: DPLL_MULT_VALUE = 242

Cortex_A8_0: GEL Output: DPLL_DIV_VALUE = 13

Cortex_A8_0: GEL Output: CORE_DPLL_CLK = 663.771 MHz

Cortex_A8_0: GEL Output: CORE_CLK = 331.8855 MHz

Cortex_A8_0: GEL Output: L3_CLK = 165.9427 MHz

Cortex_A8_0: GEL Output: MM01: mDDR Samsung K4X51323PC - 512 Mbit(64MB) on CS0, 4M x 32bit x 4Banks

Cortex_A8_0: GEL Output: common_sdram_init() completed

Cortex_A8_0: GEL Output: SDRC initilization for mDDR_Samsung_K4X51323PC completed

Cortex_A8_0: GEL Output: 19.2MHz clock configuration IIa

Cortex_A8_0: GEL Output: CORTEXA8_CORE_VERSION = 0x411FC082

Cortex_A8_0: GEL Output: Target contains version r1p2 of the CortexA8...

Cortex_A8_0: GEL Output: Read the ETM_POWER_DOWN_STATUS register...

Cortex_A8_0: GEL Output: ETM_POWER_DOWN_STATUS = 0x00000001

Cortex_A8_0: GEL Output: ETM Access is enabled!

Cortex_A8_0: GEL Output: ETM_ID = 0x410CF232

Cortex_A8_0: GEL Output: ETM Version is: 3.3v2

Cortex_A8_0: Loader: One or more sections of your program falls into a memory region that is not writable. These regions will not actually be written to the target. Check your linker configuration and/or memory map.

Cortex_A8_0: File Loader: Data verification failed at address 0x00000020 Please verify target memory and memory map.

Cortex_A8_0: Unable to terminate memory download: NULL buffer pointer at 0x3a9f

Cortex_A8_0: GEL: File: D:\Texas Instruments\ccs v5\justdemo\Debug\justdemo.out: a data verification error occurred, file load failed.

So, if anyone knows about then please let me know.

With Regards

Nitin mewada