Hi,
My customer reported an issue with DDR3 ECC test on their custom board.
The test works fine on TI IDK.
u-boot DDR3 test log on TMDSIDK574:
=> ddr ecc_err 0x80000000 0x1
Testing DDR ECC:
ECC test: Disabling DDR ECC ...
ECC test: addr 0x80000000, read data 0xfffffff, written data 0xffffffe, err pattern: 0x1, read after write data 0xffffffe
ECC test: Enabling DDR ECC ...
ECC test: addr 0x80000000, read data 0xfffffff
ECC test Status:
ECC test: 1-bit ECC err count: 0x1
u-boot DDR3 test log on custom board (ecc_test=1):
=> ddr ecc_err 0x90000000 0x1
Testing DDR ECC:
ECC test: Disabling DDR ECC ...
ECC test: addr 0x90000000, read data 0x0, written data 0x1, err pattern: 0x1, read after write data 0x1
ECC test: Enabling DDR ECC ...
ECC test Status:
ECC test: DDR ECC 2-bit error interrupted <== It should be 1-bit ECC err, but handled as 2-bit err
resetting ...
u-boot DDR3 test log on custom board (ecc_test=0):
=> ddr ecc_err 0x90000000 0x1
Testing DDR ECC:
ECC test: Disabling DDR ECC ...
ECC test: addr 0x90000000, read data 0x0, written data 0x1, err pattern: 0x1, read after write data 0x1
ECC test: Enabling DDR ECC ...
ECC test Status:
=> <== test stops here and hangs up
Software: ti-processor-sdk-linux-am57xx-evm-06.00.00.07
The DDR3 configuration on the custom board:
- only EMIF1 is used. EMIF1 connection/configuration is the same as IDK.
Board.c is changed as follows;
static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
/*
.dmm_lisa_map_2 = 0xc0600200,
.dmm_lisa_map_3 = 0x80600100,
*/
/*modify*/
.dmm_lisa_map_0 = 0x00000000,
.dmm_lisa_map_1 = 0x00000000,
.dmm_lisa_map_2 = 0x00000000,
.dmm_lisa_map_3 = 0x80600100,
.is_ma_present = 0x1
};
Are there anything to check?
Thanks and regards,
Koichiro Tashiro
