TMS320C6657: L1 cache management

Hello,

I'm working on a software which was using only one core of the c6657.
I'm now using the 2 cores and I use the shared ram + the hardware semaphores + inter-core interrupts to communicate between the 2 cores.
I have some problems with the shared buffers I have implemented and I suspect some cache problems (we use full L1 as cache and full L2 as standard RAM)

Here is how my sofware works :

Core 0 - acquire HW semaphore then invalidate L1D concerning the buffer
Core 0 - write in shared buffer (fifo like partitionned buffer)
Core 0 - write back L1D concerning the buffer then release HW semaphore
Core 0 - send inter core interrupt

Core 1 - receive inter core interrupt
Core 1 - acquire HW semaphore then invalidate L1D concerning the buffer
Core 1 - reads and delete data
Core 1 - write back L1D concerning the buffer then release HW semaphore

I have read the following post and I have some questions about the parameters for cache invalidate and cache write back
e2e.ti.com/.../446833

L1D XXX Word Count Register are 16 bits wide and my L1D is 32k.
My shared buffer is bigger than the L1D, let's say 128kiB from 0xC000000 to 0xC1FFFFF

But, when the low level layer of my software do some cache management :

1. it doesn't know which part of the buffer has been updated in MSM SRAM by the high level layer
2. and it doesn't know which part of the buffer is cached.

So, in csl CACHE_wbL1d and CACHE_invL1d what value should I use for blockPtr (L1D XXX BAR_ADDR) and byteCnt (L1D XXX Word Count Register) ?

Regards,

David