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EVMK2H: Question about DDR3B (DSP view)

Fabio Cipriani
Intellectual 910 points
Part Number: EVMK2H


Hi,

I'm  using EVMK2H Rev 4.0  

As far as I understand, reading  SPRS866G  table 8-1,   DSP can access DDR3B using both address 0x6000 0000 and  0x8000 0000,   as stated in  NOTE4: "This region is aliased of 00 8000 0000 to 00 9FFF FFFF (the first 512MB of DDR3B)"

So writing  a value  to 0x6000 0000, I expect to find the same value at 0x8000 0000  .....   but it's not happening....   

I do the following steps:

1) Connect to DSP0

2) Run the default gel file xtcievmk2x.gel

3) Write a value to 0x6000 0000 , verify the value at  0x8000 0000

what I'm doing wrong?

Thanks a lot in advance.

  • 0
    TI__Guru* 95265 points

    Hi,

    Please use JTAG to look at register 0x0800_0000 region, this is DSP core MPAX setup. I believe there is default at the boot time, mapping physical address 0x8:0000:0000 to logical address 0x8000:0000. That is 0x8000:0000 is DDR3A. Also, the GEL file also has this mapping setup.

    Regards, Eric

  • 0 in reply to lding
    Intellectual 910 points

    Thanks for the reply.

    Yes, this is the default set-up, from sprugw0c document:

    "The XMC configures MPAX segments 0 and 1 so that C66x CorePac can access system
    memory. The power up configuration is that segment 1 remaps 8000_0000 –
    FFFF_FFFF in C66x CorePac’s address space to 8:0000_0000 – 8:7FFF_FFFF in the
    system address map. This corresponds to the first 2GB of address space dedicated to
    EMIF by the MSMC controller. "

    How can I disable this configuration? I want to read/write DDR3B at address 0x8000_0000

    After boot, I wrote 0x00000000 (SEGSZ = 0, meaning segment disabled) at address 0x800_000C (XMPAX1_H) without success

    thank you.

  • 0 in reply to Fabio Cipriani
    TI__Guru* 95265 points

    Hi,

    You can do this way:

    1) connect JTAG to C66x_0, look at 0x0800_0000, then change offset 0x8 and 0xc as follows:

    This map physical address 0x0:6000:0000 (DDR3B) into logical 0x8000:0000 for 256MB.

    Then I looked at CCS memory view, 0x6000:0000, it is same as 0x8000:0000. And 8:0000:0000 is now different.

    Regards, Eric