TDA2EXEVM: Understanding Processor SDK TDA2 Cascade Mode

Also, There are two #define constant that I guess might mean the same.

CHAINS_CASCADE_RADAR_RADAR_HEIGHT defines in chains_common_cascade_ar12xx_config_mimo.c - This is the number of chirps per frame

CHAINS_RADAR_MAX_NUM_CHIRP_CFG defines in chains_radar.h - This is used in chains_common_cascade_ar12xx_config_mimo.c to create array of structure

rlChirpCfg_t   gChains_cascadeRadarChirpCfgArgsMaster[CHAINS_RADAR_MAX_NUM_CHIRP_CFG]

If we desire to change number of chirps in the chirp frame, I suppose we need to change CHAINS_CASCADE_RADAR_RADAR_HEIGHT and not CHAINS_RADAR_MAX_NUM_CHIRP_CFG. But does CHAINS_RADAR_MAX_NUM_CHIRP_CFG  also need to be changed if we change CHAINS_CASCADE_RADAR_RADAR_HEIGHT ?

Thanks,

--Khai

Hi

I will check with RADAR SDK expert & let you know.

Thanks

Gaviraju

Hi Gaviraju,

I have another question. In the ProcessorSDK_Radar_dataSheet.pdf chapter 4 where it mentioned "The height of the frame is Num of TDMA Tx antenna x Doppler Dimension". I understand the TX is chirping in a TDMA fashion from TX0 -> TX11 of all 4 sensors. What's not clear is that does each TX transmit chirp for the entire chirp frame (say if I have 128 chirps per frame) before the next TX chirps the next chirp frame OR all TXes only chirps 1 chirp round robinly and then the second and third chirps and so on...

Thanks,

--Khai

1. Master is the AWR device providing the clock to the 3 Slave devices so the 4 AWR devices can be cascaded.

2. We just allocated the structure to accommodate the maximal number of chirp configurations as place holder. In the example, we only use 10 chirp configurations.

3. txEnable is the bit mask of which Transmitter in AWR to enable.

/**
* @brief Tx enable selection bit mask \n
b0 Enable TX0 \n
0 Tx0 Disable \n
1 Tx0 Enable \n
b1 Enable TX1 \n
0 Tx1 Disable \n
1 Tx1 Enable \n
b2 Enable TX2 \n
0 Tx2 Disable \n
1 Tx2 Enable \n
Note: Maximum of only 2 TX can be turned in a chirp \n
*/
rlUInt16_t txEnable;