66AK2G12: DMA Example Code and Drivers

Hi Rahul,

Thanks for the links. It helped us create our own basic DMA low-level driver. 

We tried testing the DMA by moving data between two timer registers which worked fine without any issues.

However when we tried to move the data between two memory location on the DDR, we found that transfer was complete and interrupt occurred. But when we checked the memory locations the data was not moved. 
But when we try the same scenario with Cache disabled the data was transferred without any issue. 

Further we decided to invalidate the cache for that memory location. We decided to go with csl_cache libraries that had the API to invalidate the cache. But while executing we end up with undefined reference to _disable_interrupts(), _restore_interrupts(), asm().

We tried grepping for these function but we can't find these function definitions. 

Can you point us to the source files for these functions. It would be great if there is any example code for cache invalidation.

Also is there any other libraries/APIs to invalidate the cache.

Thanks in advance.

Krishna

Hi Eric,

We tried including the libraries but the compiler didn't support them.

By the way we are using the A15 core and not the DSP core. But when we tried to include the libs in the A15 folder "C:\ti\pdk_k2g_1_0_14\packages\ti\csl\lib\k2g\a15\release" the compiler accepted those libraries. (Screenshot attached).

But however inside cache invalidation function, we commented out interrupts disabling and restoring function and finally the code was compiled. 

But during debugging, the code hangs at the CACHE_invL1d() function. 

We also tried to manually populate the values in the L1DIBAR, L1DIWC registers. But whenever we try to access these cache registers the code hangs there. We also tried to simple read from these registers and still the code hangs in that statement.
I found the same issue with all L1D related registers like L1DCFG and L1DCC register. I could neither read or write in these registers.

Statements that I found to make the program hanging:

• CACHE_invL1d (&dstBuff1, 512, CACHE_NOWAIT);
• HW_RD_REG32(BBL1DCC);   //a write has the same result

So my query is,

1. Is there anything that I am missing while trying to access the L1D cache registers. Any special previledges that I would need to take care before accessing cache registers.

2. DMA works absolutely fine when I try to move data between peripheral's registers like timer registers. Also DMA data transfer between two DDR location was successful when I disable cache from cfg file [but the code execution time takes a big hit]. So the only option that I can opt here is cache invalidation.

But to achieve this, I am not able to access L1D cache registers which again brings me to query 1.

3. Also in the example code the source address was flushed [Edma3_CacheFlush()] and destination address was invalidated. But since we are using our custom EDMA API, pls let me know how can I achieve the cache flushing. Is there a separate APIs for flushing the cache.  

Please do let me know what should I do differently? 

With Thanks,

Krishna.

PS - In the attached figure, the red boxes show the libs that you mentioned in the earlier post. The lib files trigger error when they are linked in the project. The green boxes are the libs available for the A15.

Hi Eric,

Thanks for the help. The drivers solved the issue. 

For testing purpose we assigned both the source and destination inside the DDR.

We invalidated the destination and source before initiating DMA transfer. After DMA interrupt we read the destination registers and some registers didn't have the correct values. But after DMA interrupt we invalidated the cache address again and then reading the destination registers gave the correct values. 

So is this the right procedure for DMA, (ie)  to invalidate the cache before initiating the DMA transfer and invalidating them before reading the destination registers to verify the values.

Thanks.

Krishna.

Hi Eric,

Thanks for the help.  That solves the DMA issues. 

Regards,

Krish.