TDA4VMXEVM: VPAC VISS Node Setup

Tobias Worthmann

Prodigy 20 points

Part Number: TDA4VMXEVM

Hi TI,

I have a few questions regarding the VPAC VISS Node usage.

1. Is there host emulation available for the VPAC nodes?

2. Is is possible to configure the VISS node to receive UV as 8 bit in full resolution (not downsampled)?

3. There seems to be a bug in the VISS node creation if you pass NULL as the output2 parameter.

a) In vx_vpac_viss_target.c you call Vhwa_m2mVissParamsInit() which enables the output2 even if it is not used. This leads to an error during graph verification. I changed this by setting prms->outPrms[VHWA…].enable = FALSE in the mentioned function;

4. What is the minimal configuration to make the VISS node output something meaningful with RAW image input from RAM?

a) I have tried the following but I just receive white noise in the viss_Y12_out_img, which seems to be no surprise since the whole RFE configuration is missing in the available VISS node parameters. Where would I have to set that and is there a guide for configuring the VISS?

/* Create VISS parameters */

viss_params.sensor_dcc_id = 0; // Is this necessary?

viss_params.use_case = 0;

viss_params.ee_mode = TIVX_VPAC_VISS_EE_MODE_OFF;

viss_params.mux_output0 = TIVX_VPAC_VISS_MUX0_Y12;

viss_params.mux_output1 = 0;

viss_params.mux_output2 = 0;

viss_params.mux_output3 = 0;

viss_params.mux_output4 = 0;

viss_params.h3a_in = 0;

viss_params.h3a_aewb_af_mode = 0;

viss_params.chroma_mode = 0;

viss_params.enable_ctx = 0;

viss_params.bypass_glbce = 1;

viss_params.bypass_nsf4 = 1;

viss_configuration = vxCreateUserDataObject(… &viss_params);

/* Create images */

raw_params.width = width;

raw_params.height = height;

raw_params.num_exposures = 1;

raw_params.line_interleaved = vx_false_e;

raw_params.format[0].pixel_container = TIVX_RAW_IMAGE_16_BIT;

raw_params.format[0].msb = msb;

raw_params.meta_height_before = 0;

raw_params.meta_height_after = 0;

raw_img = tivxCreateRawImage(... &raw_params);

viss_Y12_out_img = vxCreateImage(... width, height, VX_DF_IMAGE_U16);

/* Fill raw buffer from RAM */

tivxMapRawImagePatch(raw_img,

&rect, // {0,0,width,height}

&map_id,

&user_addr,

&user_ptr,

VX_READ_AND_WRITE,

VX_MEMORY_TYPE_HOST ,

TIVX_RAW_IMAGE_PIXEL_BUFFER);

for (lines) { // line by line copy

memcpy(user_ptr, image_data_from_RAM, line_width);

}

tivxUnmapRawImagePatch(raw_img, map_id);

/* Node creation */

viss_configuration = tivxVpacVissNode(graph,

viss_configuration,

NULL,

raw_img,

viss_Y12_out_img,

NULL,

NULL);

Best Regards,

Tobi

over 5 years ago

0 Mayank Mangla over 5 years ago

TI__Mastermind 24525 points

1. Is there host emulation available for the VPAC nodes?

There is limited support for host emulation mode. Please refer to test_vpac_viss conformance test.

2. Is is possible to configure the VISS node to receive UV as 8 bit in full resolution (not downsampled)?

Do you mean YUV444?

3. There seems to be a bug in the VISS node creation if you pass NULL as the output2 parameter.

Thanks for reporting it. We will look into it.

4. What is the minimal configuration to make the VISS node output something meaningful with RAW image input from RAM?

Most of the configuration comes from DCC (Dynamic Camera Configuration) files . DCC provides RFE and everything else needed for VISS to correctly process the RAW image. DCC support is not available in the conformance tests. Please refer to single camera app in basic_demos to see an example of DCC.

0 Vivek Malhotra65 over 5 years ago in reply to Mayank Mangla

Prodigy 130 points

Hi Mayank,

We have an additional question.

Our first node (capture) is configured in CSIRX_CH_TYPE_CAPT mode, so the frames are captured in DDR and then we connect the second node viss in our openvx graph. I hope this config shall work ?

Later we woud like to test the OTF mode by changing the capture driver to CSIRX_CH_TYPE_OTF, please let me know apart from this change is there anything else to be changed in the graph for OTF mode ? Is there any example which we can refer ?

Regards

Vivek

0 Tobias Worthmann over 5 years ago in reply to Mayank Mangla

Prodigy 20 points

Hi Mayank,

2. Is is possible to configure the VISS node to receive UV as 8 bit in full resolution (not downsampled)?

Do you mean YUV444?

Yes, exactly.

4. What is the minimal configuration to make the VISS node output something meaningful with RAW image input from RAM?

I guess the challenge will be to add a custom sensor configuration. We'll have a look at it and come back to you if we have specific questions.

Best Regards,

Tobi

0 Mayank Mangla over 5 years ago in reply to Vivek Malhotra65

TI__Mastermind 24525 points

Our first node (capture) is configured in CSIRX_CH_TYPE_CAPT mode, so the frames are captured in DDR and then we connect the second node viss in our openvx graph. I hope this config shall work ?

[Mayank] This is the default mode and this will work.

[Mayank] There is currently no example of OTF mode. Let's talk again when you are ready to try this.

0 Vivek Malhotra65 over 5 years ago in reply to Mayank Mangla

Prodigy 130 points

Hello Mayank,

Sorry, I had to take down the post for now. I would still ask for the 16>12 bit LUT algo used and viss simulator.

I can repost the original text after clearance from our department.

Thanks

0 Mayank Mangla over 5 years ago in reply to Vivek Malhotra65

TI__Mastermind 24525 points

Vivek,

Are you planning to work on the target or host emulation?

Regards,

Mayank

0 Vivek Malhotra65 over 5 years ago in reply to Mayank Mangla

Prodigy 130 points

So far for camera integration I worked on hw,

If there is host emu for VISS available ? please let me know where and how in PSDK can i use it ? Would be great to use it

thanks

0 Mayank Mangla over 5 years ago in reply to Vivek Malhotra65

TI__Mastermind 24525 points

Vikram,

Host emulation does not support the full chain of sensor capture, ISP, 2A, DCC etc.

Working on target is better. Please create a new post with your detailed questions when you get the clearance.

I am hoping we can close this thread for now..

Regards,

Mayank

0 Dominic Fellner over 5 years ago in reply to Tobias Worthmann

Prodigy 200 points

Tobias Worthmann said:

2. Is is possible to configure the VISS node to receive UV as 8 bit in full resolution (not downsampled)?

Do you mean YUV444?

Yes, exactly.

Actually, we want to get UV interleaved in 8 bit with full resolution. We only found NV12 or UV8 in subsampled resolution. Is it possible to get UV8 interleaved with full resolution in 8bit depth?

0 Brijesh Jadav over 5 years ago in reply to Dominic Fellner

TI__Guru**** 487415 points

VISS does not support YUV444, ie full resolution for U & V.

Rgds,

Brijesh

0 Vivek Malhotra65 over 5 years ago in reply to Mayank Mangla

Prodigy 130 points

Thanks, would you please let me know about the tone mapping algo used for 16 to 12 bit ? That would close the thread and we can start new thread later on for other questions.

0 Mayank Mangla over 5 years ago in reply to Vivek Malhotra65

TI__Mastermind 24525 points

Hello Tobias,

Tone mapping block is documented in the NDA TRM (not public TRM). Please refer to chapter 6.10.4.5

Regards,

Mayank

0 Vivek Malhotra65 over 5 years ago in reply to Mayank Mangla

Prodigy 130 points

Hi Mayank,

I had seen section 6.10.4.6.3.3.3.4, LUT based 12 bit to 8 bit downsampling, this will be for luma downsampling. I wanted to know the LUT at the entry of FCP module to tone map 14 bit to 12 bit, which would later be processed by Flex-CFA.

At 6.10.4.5, there is reference to GLBCE, but I dont use it. i would be interested in the FCP module LUT

Thanks

0 Mayank Mangla over 5 years ago in reply to Vivek Malhotra65

TI__Mastermind 24525 points

Hello Vivek,

You can bypass GLBCE and use FCP LUT. If you have any questions about this please request your TI representative to connect you to us.

Regards,

Mayank

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TDA4VMXEVM: VPAC VISS Node Setup